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1b216a8718
Subregister definitions are considered uses for the purpose of tracking liveness of the whole register. At the same time, when calculating live interval subranges, subregister defs should not be treated as uses. Differential Revision: https://reviews.llvm.org/D24190 llvm-svn: 280532
116 lines
7.7 KiB
LLVM
116 lines
7.7 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck %s
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; REQUIRES: asserts
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;
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; This test used to crash with the following assertion:
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; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.
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;
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; This was related to incorrectly calculating subregister live ranges
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; (i.e. live interval subranges): subregister defs are not uses for that
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; purpose.
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;
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; Check for a valid output.
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; CHECK: image_sample_c
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target triple = "amdgcn--"
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@ddxy_lds = external addrspace(3) global [64 x i32]
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define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg, [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg1, [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg2, [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg3, [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg4, float inreg %arg5, i32 inreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, <2 x i32> %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, i32 %arg20, float %arg21, i32 %arg22) #0 {
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main_body:
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%tmp = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %arg6, <2 x i32> %arg8)
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%tmp23 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp24 = extractelement <4 x float> %tmp23, i32 3
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%tmp25 = fmul float %tmp24, undef
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%tmp26 = fmul float undef, %tmp
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%tmp27 = fadd float %tmp26, undef
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%tmp28 = bitcast float %tmp27 to i32
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%tmp29 = insertelement <4 x i32> undef, i32 %tmp28, i32 0
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%tmp30 = insertelement <4 x i32> %tmp29, i32 0, i32 1
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%tmp31 = insertelement <4 x i32> %tmp30, i32 undef, i32 2
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%tmp32 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %tmp31, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp33 = extractelement <4 x float> %tmp32, i32 0
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%tmp34 = fadd float undef, %tmp33
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%tmp35 = fadd float %tmp34, undef
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%tmp36 = fadd float %tmp35, undef
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%tmp37 = fadd float %tmp36, undef
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%tmp38 = fadd float %tmp37, undef
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%tmp39 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp40 = extractelement <4 x float> %tmp39, i32 0
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%tmp41 = extractelement <4 x float> %tmp39, i32 1
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%tmp42 = extractelement <4 x float> %tmp39, i32 2
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%tmp43 = extractelement <4 x float> %tmp39, i32 3
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%tmp44 = fmul float %tmp40, undef
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%tmp45 = fmul float %tmp41, undef
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%tmp46 = fmul float %tmp42, undef
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%tmp47 = fmul float %tmp43, undef
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%tmp48 = fadd float undef, %tmp44
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%tmp49 = fadd float undef, %tmp45
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%tmp50 = bitcast float %tmp27 to i32
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%tmp51 = bitcast float %tmp48 to i32
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%tmp52 = bitcast float %tmp49 to i32
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%tmp53 = insertelement <4 x i32> undef, i32 %tmp50, i32 0
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%tmp54 = insertelement <4 x i32> %tmp53, i32 %tmp51, i32 1
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%tmp55 = insertelement <4 x i32> %tmp54, i32 %tmp52, i32 2
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%tmp56 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %tmp55, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp57 = extractelement <4 x float> %tmp56, i32 0
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%tmp58 = fadd float %tmp38, %tmp57
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%tmp59 = fadd float undef, %tmp46
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%tmp60 = fadd float undef, %tmp47
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%tmp61 = bitcast float %tmp59 to i32
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%tmp62 = bitcast float %tmp60 to i32
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%tmp63 = insertelement <4 x i32> undef, i32 %tmp61, i32 1
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%tmp64 = insertelement <4 x i32> %tmp63, i32 %tmp62, i32 2
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%tmp65 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %tmp64, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp66 = extractelement <4 x float> %tmp65, i32 0
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%tmp67 = fadd float %tmp58, %tmp66
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%tmp68 = fmul float %tmp67, 1.250000e-01
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%tmp69 = fmul float %tmp68, undef
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%tmp70 = fcmp une float %tmp69, 0.000000e+00
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br i1 %tmp70, label %IF26, label %ENDIF25
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IF26: ; preds = %main_body
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%tmp71 = bitcast float %tmp27 to i32
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%tmp72 = insertelement <4 x i32> undef, i32 %tmp71, i32 0
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br label %LOOP
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ENDIF25: ; preds = %IF29, %main_body
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%.4 = phi float [ %tmp84, %IF29 ], [ %tmp68, %main_body ]
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%tmp73 = fadd float %.4, undef
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%tmp74 = call float @llvm.AMDGPU.clamp.(float %tmp73, float 0.000000e+00, float 1.000000e+00)
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%tmp75 = fmul float undef, %tmp74
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%tmp76 = fmul float %tmp75, undef
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%tmp77 = fadd float %tmp76, undef
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%tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, float %tmp77, 11
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%tmp79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp78, float undef, 12
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%tmp80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp79, float undef, 13
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%tmp81 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp80, float %tmp25, 14
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%tmp82 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp81, float undef, 15
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%tmp83 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp82, float %arg21, 24
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ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp83
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LOOP: ; preds = %ENDIF28, %IF26
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%.5 = phi float [ undef, %IF26 ], [ %tmp89, %ENDIF28 ]
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br i1 false, label %IF29, label %ENDIF28
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IF29: ; preds = %LOOP
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%tmp84 = fmul float %.5, 3.125000e-02
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br label %ENDIF25
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ENDIF28: ; preds = %LOOP
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%tmp85 = insertelement <4 x i32> %tmp72, i32 undef, i32 1
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%tmp86 = insertelement <4 x i32> %tmp85, i32 undef, i32 2
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%tmp87 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %tmp86, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp88 = extractelement <4 x float> %tmp87, i32 0
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%tmp89 = fadd float undef, %tmp88
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br label %LOOP
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}
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declare float @llvm.AMDGPU.clamp.(float, float, float) #1
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declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
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declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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attributes #0 = { "InitialPSInputAddr"="36983" "target-cpu"="tonga" }
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attributes #1 = { nounwind readnone }
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