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fdd124178e
Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
40 lines
1.3 KiB
LLVM
40 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.s = type { i32, i32 }
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declare void @bar(i32*, i32*) #0
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define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 {
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entry:
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%0 = zext i32 %n to i64
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%vla = alloca i32, i64 %0, align 128
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%vla1 = alloca i32, i64 %0, align 128
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%a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
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%1 = load i32* %a2, align 4, !tbaa !0
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store i32 %1, i32* %vla1, align 128, !tbaa !0
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%b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
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%2 = load i32* %b, align 4, !tbaa !0
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%arrayidx3 = getelementptr inbounds i32* %vla1, i64 1
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store i32 %2, i32* %arrayidx3, align 4, !tbaa !0
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call void @bar(i32* %vla1, i32* %vla) #0
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ret void
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; CHECK-LABEL: @goo
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; CHECK-DAG: li [[REG1:[0-9]+]], -128
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; CHECK-DAG: neg [[REG2:[0-9]+]],
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; CHECK: and [[REG1]], [[REG2]], [[REG1]]
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; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
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; CHECK: blr
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}
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attributes #0 = { nounwind }
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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