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d9bf037744
Summary: The main challenge in lowering kernel arguments for AMDGPU is determing the memory type of the argument. The generic calling convention code assumes that only legal register types can be stored in memory, but this is not the case for AMDGPU. This consolidates all the logic AMDGPU uses for deducing memory types into a single function. This will make it much easier to support different ABIs in the future. Reviewers: arsenm Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24614 llvm-svn: 281781
325 lines
12 KiB
C++
325 lines
12 KiB
C++
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class AMDGPUMachineFunction;
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class AMDGPUSubtarget;
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class MachineRegisterInfo;
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class AMDGPUTargetLowering : public TargetLowering {
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protected:
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const AMDGPUSubtarget *Subtarget;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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protected:
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bool shouldCombineMemoryType(EVT VT) const;
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SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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uint32_t ValLo, uint32_t ValHi) const;
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SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
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SDValue RHS, DAGCombinerInfo &DCI) const;
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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/// Return 64-bit value Op as two 32-bit integers.
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std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
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SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector load into 2 loads of half the vector.
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SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into 2 stores of half the vector.
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SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
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void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const;
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void analyzeFormalArgumentsCompute(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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void AnalyzeFormalArguments(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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void AnalyzeReturn(CCState &State,
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const SmallVectorImpl<ISD::OutputArg> &Outs) const;
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public:
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AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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bool isFAbsFree(EVT VT) const override;
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bool isFNegFree(EVT VT) const override;
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bool isTruncateFree(EVT Src, EVT Dest) const override;
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bool isTruncateFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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MVT getVectorIdxTy(const DataLayout &) const override;
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bool isSelectSupported(SelectSupportKind) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override;
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bool shouldReduceLoadWidth(SDNode *Load,
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ISD::LoadExtType ExtType,
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EVT ExtVT) const override;
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bool isLoadBitCastBeneficial(EVT, EVT) const final;
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bool storeOfVectorConstantIsCheap(EVT MemVT,
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unsigned NumElem,
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unsigned AS) const override;
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bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
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SDValue RHS, SDValue True, SDValue False,
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SDValue CC, DAGCombinerInfo &DCI) const;
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const char* getTargetNodeName(unsigned Opcode) const override;
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bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
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return true;
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}
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SDValue getRsqrtEstimate(SDValue Operand,
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DAGCombinerInfo &DCI,
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unsigned &RefinementSteps,
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bool &UseOneConstNR) const override;
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SDValue getRecipEstimate(SDValue Operand,
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DAGCombinerInfo &DCI,
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unsigned &RefinementSteps) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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SelectionDAG &DAG) const = 0;
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/// \brief Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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enum ImplicitParameter {
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FIRST_IMPLICIT,
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GRID_DIM = FIRST_IMPLICIT,
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GRID_OFFSET,
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};
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/// \brief Helper function that returns the byte offset of the given
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/// type of implicit parameter.
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uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
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const ImplicitParameter Param) const;
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};
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namespace AMDGPUISD {
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enum NodeType : unsigned {
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // Function call based on a single integer
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UMUL, // 32bit unsigned multiplication
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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ENDPGM,
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RETURN,
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DWORDADDR,
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FRACT,
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CLAMP,
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// This is SETCC with the full mask result which is used for a compare with a
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// result bit per item in the wavefront.
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SETCC,
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// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
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// Denormals handled on some parts.
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COS_HW,
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SIN_HW,
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FMAX_LEGACY,
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FMIN_LEGACY,
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FMAX3,
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SMAX3,
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UMAX3,
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FMIN3,
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SMIN3,
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UMIN3,
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FMED3,
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SMED3,
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UMED3,
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URECIP,
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DIV_SCALE,
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DIV_FMAS,
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DIV_FIXUP,
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TRIG_PREOP, // 1 ULP max error for f64
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// RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
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// For f64, max error 2^29 ULP, handles denormals.
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RCP,
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RSQ,
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RCP_LEGACY,
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RSQ_LEGACY,
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FMUL_LEGACY,
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RSQ_CLAMP,
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LDEXP,
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FP_CLASS,
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DOT4,
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CARRY,
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BORROW,
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BFE_U32, // Extract range of bits with zero extension to 32-bits.
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BFE_I32, // Extract range of bits with sign extension to 32-bits.
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BFI, // (src0 & src1) | (~src0 & src2)
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BFM, // Insert a range of bits into a 32-bit word.
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FFBH_U32, // ctlz with -1 if input is zero.
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FFBH_I32,
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MUL_U24,
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MUL_I24,
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MULHI_U24,
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MULHI_I24,
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MAD_U24,
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MAD_I24,
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MUL_LOHI_I24,
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MUL_LOHI_U24,
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TEXTURE_FETCH,
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EXPORT,
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CONST_ADDRESS,
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REGISTER_LOAD,
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REGISTER_STORE,
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LOAD_INPUT,
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SAMPLE,
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SAMPLEB,
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SAMPLED,
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SAMPLEL,
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// These cvt_f32_ubyte* nodes need to remain consecutive and in order.
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CVT_F32_UBYTE0,
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CVT_F32_UBYTE1,
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CVT_F32_UBYTE2,
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CVT_F32_UBYTE3,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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/// |X |Y|Z|W|
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/// T0|v.x| | | |
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/// T1|v.y| | | |
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/// T2|v.z| | | |
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/// T3|v.w| | | |
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BUILD_VERTICAL_VECTOR,
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/// Pointer to the start of the shader's constant data.
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CONST_DATA_PTR,
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SENDMSG,
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INTERP_MOV,
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INTERP_P1,
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INTERP_P2,
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PC_ADD_REL_OFFSET,
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KILL,
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FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
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STORE_MSKOR,
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LOAD_CONSTANT,
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TBUFFER_STORE_FORMAT,
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ATOMIC_CMP_SWAP,
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ATOMIC_INC,
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ATOMIC_DEC,
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LAST_AMDGPU_ISD_NUMBER
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};
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} // End namespace AMDGPUISD
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} // End namespace llvm
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#endif
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