David Green f2589e2340 [ARM] Allow tail predication of VLDn ... VLD2/4 instructions cannot be predicated, so we cannot tail predicate them from autovec. From intrinsics though, they should be valid as they will just end up loading extra values into off vector lanes, not effecting the on lanes. The same is true for loads in general where so long as we are not using the other vector lanes, an unpredicated load can be converted to a predicated one. This marks VLD2 and VLD4 instructions as validForTailPredication and allows any unpredicated load in tail predication loop, which seems to be valid given the other checks we have. Differential Revision: https://reviews.llvm.org/D86022		2020-08-18 17:15:45 +01:00
..
AArch64	Make llvm::StringRef to std::string conversions explicit.	2020-01-28 23:25:25 +01:00
AMDGPU	[NFC][AMDGPU] Fix cmake when LLVM is a subproject	2020-04-22 14:25:44 +02:00
ARM	[ARM] Allow tail predication of VLDn	2020-08-18 17:15:45 +01:00
PowerPC	[NFC][PowerPC] Remove unnecessary link components.	2020-01-16 21:22:51 -05:00
WebAssembly	CMake: Make most target symbols hidden by default	2020-01-14 19:46:52 -08:00
X86	[PGO][PGSO] Distinguish queries from unit tests and explicitly enable for the existing IR passes only. NFC.	2019-12-04 09:35:50 -08:00
CMakeLists.txt