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Summary: We now have two sets of generated TableGen files, one for R600 and one for GCN, so each sub-target now has its own tables of instructions, registers, ISel patterns, etc. This should help reduce compile time since each sub-target now only has to consider information that is specific to itself. This will also help prevent the R600 sub-target from slowing down new features for GCN, like disassembler support, GlobalISel, etc. Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46365 llvm-svn: 335942
28 lines
779 B
C++
28 lines
779 B
C++
//===-- R600MCTargetDesc.cpp - R600 Target Descriptions -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This file provides R600 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "R600GenInstrInfo.inc"
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MCInstrInfo *llvm::createR600MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitR600MCInstrInfo(X);
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return X;
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}
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