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For context, the proposed RISC-V bit manipulation extension has a subset of instructions which require one of two SubtargetFeatures to be enabled, 'zbb' or 'zbp', and there is no defined feature which both of these can imply to use as a constraint either (see comments in D65649). AssemblerPredicates allow multiple SubtargetFeatures to be declared in the "AssemblerCondString" field, separated by commas, and this means that the two features must both be enabled. There is no equivalent to say that _either_ feature X or feature Y must be enabled, short of creating a dummy SubtargetFeature for this purpose and having features X and Y imply the new feature. To solve the case where X or Y is needed without adding a new feature, and to better match a typical TableGen style, this replaces the existing "AssemblerCondString" with a dag "AssemblerCondDag" which represents the same information. Two operators are defined for use with AssemblerCondDag, "all_of", which matches the current behaviour, and "any_of", which adds the new proposed ORing features functionality. This was originally proposed in the RFC at http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html Changes to all current backends are mechanical to support the replaced functionality, and are NFCI. At this stage, it is illegal to combine features with ands and ors in a single AssemblerCondDag. I suspect this case is sufficiently rare that adding more complex changes to support it are unnecessary. Differential Revision: https://reviews.llvm.org/D74338
33 lines
963 B
TableGen
33 lines
963 B
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
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// Check that we don't generate invalid code of the form "( && Cond2)" when
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// emitting AssemblerPredicate conditions. In the example below, the invalid
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// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def AssemblerCondition2 : SubtargetFeature<"cond2", "cond2", "true", "">;
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def Pred1 : Predicate<"Condition1">;
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def Pred2 : Predicate<"Condition2">,
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AssemblerPredicate<(all_of AssemblerCondition2)>;
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def foo : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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field bits<16> Inst;
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let Inst = 0xAAAA;
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let AsmString = "foo";
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field bits<16> SoftFail = 0;
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// This is the important bit:
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let Predicates = [Pred1, Pred2];
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}
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// CHECK: return (Bits[arch::AssemblerCondition2]);
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