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cc2de8bfa9
Summary: This patch depends on D89846. We have the patterns to fold 2 RLWINMs in ppc-mi-peephole, while some RLWINM will be generated after RA, for example rGc4690b007743. If the RLWINM generated after RA followed by another RLWINM, we expect to perform the optimization after RA, too. Reviewed By: shchenz, steven.zhang Differential Revision: https://reviews.llvm.org/D89855
660 lines
30 KiB
C++
660 lines
30 KiB
C++
//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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#include "PPCRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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/// PPCII - This namespace holds all of the PowerPC target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// PPC.td and PPCInstrFormats.td.
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namespace PPCII {
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enum {
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// PPC970 Instruction Flags. These flags describe the characteristics of the
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// PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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// raw machine instructions.
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/// PPC970_First - This instruction starts a new dispatch group, so it will
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/// always be the first one in the group.
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PPC970_First = 0x1,
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/// PPC970_Single - This instruction starts a new dispatch group and
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift
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};
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enum PPC970_Unit {
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/// These are the various PPC970 execution unit pipelines. Each instruction
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/// is one of these.
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PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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};
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enum {
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/// Shift count to bypass PPC970 flags
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NewDef_Shift = 6,
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/// This instruction is an X-Form memory operation.
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XFormMemOp = 0x1 << NewDef_Shift,
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/// This instruction is prefixed.
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Prefixed = 0x1 << (NewDef_Shift+1)
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};
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} // end namespace PPCII
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// Instructions that have an immediate form might be convertible to that
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// form if the correct input is a result of a load immediate. In order to
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// know whether the transformation is special, we might need to know some
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// of the details of the two forms.
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struct ImmInstrInfo {
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// Is the immediate field in the immediate form signed or unsigned?
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uint64_t SignedImm : 1;
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// Does the immediate need to be a multiple of some value?
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uint64_t ImmMustBeMultipleOf : 5;
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// Is R0/X0 treated specially by the original r+r instruction?
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// If so, in which operand?
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uint64_t ZeroIsSpecialOrig : 3;
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// Is R0/X0 treated specially by the new r+i instruction?
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// If so, in which operand?
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uint64_t ZeroIsSpecialNew : 3;
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// Is the operation commutative?
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uint64_t IsCommutative : 1;
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// The operand number to check for add-immediate def.
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uint64_t OpNoForForwarding : 3;
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// The operand number for the immediate.
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uint64_t ImmOpNo : 3;
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// The opcode of the new instruction.
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uint64_t ImmOpcode : 16;
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// The size of the immediate.
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uint64_t ImmWidth : 5;
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// The immediate should be truncated to N bits.
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uint64_t TruncateImmTo : 5;
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// Is the instruction summing the operand
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uint64_t IsSummingOperands : 1;
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};
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// Information required to convert an instruction to just a materialized
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// immediate.
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struct LoadImmediateInfo {
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unsigned Imm : 16;
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unsigned Is64Bit : 1;
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unsigned SetCR : 1;
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};
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// Index into the OpcodesForSpill array.
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enum SpillOpcodeKey {
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SOK_Int4Spill,
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SOK_Int8Spill,
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SOK_Float8Spill,
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SOK_Float4Spill,
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SOK_CRSpill,
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SOK_CRBitSpill,
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SOK_VRVectorSpill,
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SOK_VSXVectorSpill,
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SOK_VectorFloat8Spill,
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SOK_VectorFloat4Spill,
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SOK_SpillToVSR,
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SOK_SPESpill,
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SOK_LastOpcodeSpill // This must be last on the enum.
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};
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// Define list of load and store spill opcodes.
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#define Pwr8LoadOpcodes \
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{ \
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PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
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PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
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PPC::SPILLTOVSR_LD, PPC::EVLDD \
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}
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#define Pwr9LoadOpcodes \
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{ \
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PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
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PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
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PPC::DFLOADf32, PPC::SPILLTOVSR_LD \
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}
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#define Pwr8StoreOpcodes \
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{ \
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PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
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PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
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PPC::SPILLTOVSR_ST, PPC::EVSTDD \
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}
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#define Pwr9StoreOpcodes \
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{ \
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PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
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PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
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PPC::SPILLTOVSR_ST \
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}
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// Initialize arrays for load and store spill opcodes on supported subtargets.
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#define StoreOpcodesForSpill \
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{ Pwr8StoreOpcodes, Pwr9StoreOpcodes }
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#define LoadOpcodesForSpill \
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{ Pwr8LoadOpcodes, Pwr9LoadOpcodes }
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class PPCSubtarget;
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCSubtarget &Subtarget;
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const PPCRegisterInfo RI;
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const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] =
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StoreOpcodesForSpill;
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const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] =
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LoadOpcodesForSpill;
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void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
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int FrameIdx, const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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// Replace the instruction with single LI if possible. \p DefMI must be LI or
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// LI8.
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bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
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unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
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// If the inst is imm-form and its register operand is produced by a ADDI, put
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// the imm into the inst directly and remove the ADDI if possible.
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bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
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unsigned OpNoForForwarding) const;
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// If the inst is x-form and has imm-form and one of its operand is produced
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// by a LI, put the imm into the inst directly and remove the LI if possible.
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bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned ConstantOpNo,
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MachineInstr &DefMI) const;
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// If the inst is x-form and has imm-form and one of its operand is produced
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// by an add-immediate, try to transform it when possible.
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bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned ConstantOpNo, MachineInstr &DefMI,
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bool KillDefMI) const;
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// Try to find that, if the instruction 'MI' contains any operand that
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// could be forwarded from some inst that feeds it. If yes, return the
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// Def of that operand. And OpNoForForwarding is the operand index in
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// the 'MI' for that 'Def'. If we see another use of this Def between
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// the Def and the MI, SeenIntermediateUse becomes 'true'.
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MachineInstr *getForwardingDefMI(MachineInstr &MI,
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unsigned &OpNoForForwarding,
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bool &SeenIntermediateUse) const;
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// Can the user MI have it's source at index \p OpNoForForwarding
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// forwarded from an add-immediate that feeds it?
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bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
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unsigned OpNoForForwarding) const;
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bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
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const ImmInstrInfo &III,
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MachineOperand *&ImmMO,
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MachineOperand *&RegMO) const;
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bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
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const MachineInstr &DefMI,
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const ImmInstrInfo &III,
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int64_t &Imm,
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int64_t BaseImm = 0) const;
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bool isRegElgibleForForwarding(const MachineOperand &RegMO,
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const MachineInstr &DefMI,
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const MachineInstr &MI, bool KillDefMI,
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bool &IsFwdFeederRegKilled) const;
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unsigned getSpillTarget() const;
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const unsigned *getStoreOpcodesForSpillArray() const;
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const unsigned *getLoadOpcodesForSpillArray() const;
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int16_t getFMAOpIdxInfo(unsigned Opcode) const;
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void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
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virtual void anchor();
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protected:
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/// Commutes the operands in the given instruction.
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/// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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///
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/// Do not call this method for a non-commutable instruction or for
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/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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/// Even though the instruction is commutable, the method may still
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/// fail to commute the operands, null pointer is returned in such cases.
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///
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/// For example, we can commute rlwimi instructions, but only if the
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/// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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public:
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explicit PPCInstrInfo(PPCSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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bool isXFormMemOp(unsigned Opcode) const {
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return get(Opcode).TSFlags & PPCII::XFormMemOp;
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}
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bool isPrefixed(unsigned Opcode) const {
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return get(Opcode).TSFlags & PPCII::Prefixed;
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}
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static bool isSameClassPhysRegCopy(unsigned Opcode) {
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unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
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PPC::VOR, PPC::XXLOR, PPC::XXLORf,
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PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
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PPC::EVOR, -1U};
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for (int i = 0; CopyOpcodes[i] != -1U; i++)
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if (Opcode == CopyOpcodes[i])
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return true;
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return false;
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}
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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const ScheduleDAG *DAG) const override;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr &MI,
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unsigned *PredCost = nullptr) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr &DefMI, unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const override {
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return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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UseNode, UseIdx);
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}
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bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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const MachineInstr &DefMI,
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unsigned DefIdx) const override {
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// Machine LICM should hoist all instructions in low-register-pressure
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// situations; none are sufficiently free to justify leaving in a loop
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// body.
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return false;
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}
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bool useMachineCombiner() const override {
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return true;
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}
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/// When getMachineCombinerPatterns() finds patterns, this function generates
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/// the instructions that could replace the original code sequence
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void genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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/// Return true when there is potentially a faster code sequence for a fma
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/// chain ending in \p Root. All potential patterns are output in the \p
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/// P array.
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bool getFMAPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &P) const;
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in <Root>. All potential patterns are
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/// output in the <Pattern> array.
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bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &P) const override;
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bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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/// On PowerPC, we try to reassociate FMA chain which will increase
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/// instruction size. Set extension resource length limit to 1 for edge case.
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/// Resource Length is calculated by scaled resource usage in getCycles().
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/// Because of the division in getCycles(), it returns different cycles due to
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/// legacy scaled resource usage. So new resource length may be same with
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/// legacy or 1 bigger than legacy.
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/// We need to execlude the 1 bigger case even the resource length is not
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/// perserved for more FMA chain reassociations on PowerPC.
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int getExtendResourceLenLimit() const override { return 1; }
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void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
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MachineInstr &NewMI1,
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MachineInstr &NewMI2) const override;
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void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI,
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Register &SrcReg, Register &DstReg,
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unsigned &SubIdx) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AAResults *AA) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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// Select analysis.
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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Register, Register, Register, int &, int &,
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int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, Register DstReg,
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ArrayRef<MachineOperand> Cond, Register TrueReg,
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Register FalseReg) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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// Emits a register spill without updating the register class for vector
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// registers. This ensures that when we spill a vector register the
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// element order in the register is the same as it was in memory.
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void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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// Emits a register reload without updating the register class for vector
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// registers. This ensures that when we reload a vector register the
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// element order in the register is the same as it was in memory.
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void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
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unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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MachineRegisterInfo *MRI) const override;
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bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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Register Reg) const;
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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|
bool isProfitableToIfCvt(MachineBasicBlock &MBB,
|
|
unsigned NumCycles, unsigned ExtraPredCycles,
|
|
BranchProbability Probability) const override {
|
|
return true;
|
|
}
|
|
|
|
bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
|
|
unsigned NumT, unsigned ExtraT,
|
|
MachineBasicBlock &FMBB,
|
|
unsigned NumF, unsigned ExtraF,
|
|
BranchProbability Probability) const override;
|
|
|
|
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
|
|
BranchProbability Probability) const override {
|
|
return true;
|
|
}
|
|
|
|
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
|
|
MachineBasicBlock &FMBB) const override {
|
|
return false;
|
|
}
|
|
|
|
// Predication support.
|
|
bool isPredicated(const MachineInstr &MI) const override;
|
|
|
|
bool isSchedulingBoundary(const MachineInstr &MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const override;
|
|
|
|
bool PredicateInstruction(MachineInstr &MI,
|
|
ArrayRef<MachineOperand> Pred) const override;
|
|
|
|
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
|
ArrayRef<MachineOperand> Pred2) const override;
|
|
|
|
bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
|
|
bool SkipDead) const override;
|
|
|
|
// Comparison optimization.
|
|
|
|
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
|
|
Register &SrcReg2, int &Mask, int &Value) const override;
|
|
|
|
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
|
|
Register SrcReg2, int Mask, int Value,
|
|
const MachineRegisterInfo *MRI) const override;
|
|
|
|
|
|
/// Return true if get the base operand, byte offset of an instruction and
|
|
/// the memory width. Width is the size of memory that is being
|
|
/// loaded/stored (e.g. 1, 2, 4, 8).
|
|
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
|
|
const MachineOperand *&BaseOp,
|
|
int64_t &Offset, unsigned &Width,
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
/// Get the base operand and byte offset of an instruction that reads/writes
|
|
/// memory.
|
|
bool getMemOperandsWithOffsetWidth(
|
|
const MachineInstr &LdSt,
|
|
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
|
|
bool &OffsetIsScalable, unsigned &Width,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
|
|
/// Returns true if the two given memory operations should be scheduled
|
|
/// adjacent.
|
|
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
|
|
ArrayRef<const MachineOperand *> BaseOps2,
|
|
unsigned NumLoads, unsigned NumBytes) const override;
|
|
|
|
/// Return true if two MIs access different memory addresses and false
|
|
/// otherwise
|
|
bool
|
|
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
|
|
const MachineInstr &MIb) const override;
|
|
|
|
/// GetInstSize - Return the number of bytes of code the specified
|
|
/// instruction may be. This returns the maximum number of bytes.
|
|
///
|
|
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
|
|
|
|
void getNoop(MCInst &NopInst) const override;
|
|
|
|
std::pair<unsigned, unsigned>
|
|
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
getSerializableBitmaskMachineOperandTargetFlags() const override;
|
|
|
|
// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
|
|
bool expandVSXMemPseudo(MachineInstr &MI) const;
|
|
|
|
// Lower pseudo instructions after register allocation.
|
|
bool expandPostRAPseudo(MachineInstr &MI) const override;
|
|
|
|
static bool isVFRegister(unsigned Reg) {
|
|
return Reg >= PPC::VF0 && Reg <= PPC::VF31;
|
|
}
|
|
static bool isVRRegister(unsigned Reg) {
|
|
return Reg >= PPC::V0 && Reg <= PPC::V31;
|
|
}
|
|
const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
|
|
static int getRecordFormOpcode(unsigned Opcode);
|
|
|
|
bool isTOCSaveMI(const MachineInstr &MI) const;
|
|
|
|
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
|
|
const unsigned PhiDepth) const;
|
|
|
|
/// Return true if the output of the instruction is always a sign-extended,
|
|
/// i.e. 0 to 31-th bits are same as 32-th bit.
|
|
bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
|
|
return isSignOrZeroExtended(MI, true, depth);
|
|
}
|
|
|
|
/// Return true if the output of the instruction is always zero-extended,
|
|
/// i.e. 0 to 31-th bits are all zeros
|
|
bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
|
|
return isSignOrZeroExtended(MI, false, depth);
|
|
}
|
|
|
|
bool convertToImmediateForm(MachineInstr &MI,
|
|
MachineInstr **KilledDef = nullptr) const;
|
|
bool foldFrameOffset(MachineInstr &MI) const;
|
|
bool simplifyRotateAndMaskInstr(MachineInstr &MI,
|
|
MachineInstr *&ToErase) const;
|
|
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
|
|
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
|
|
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
|
|
unsigned &XFormOpcode,
|
|
int64_t &OffsetOfImmInstr,
|
|
ImmInstrInfo &III) const;
|
|
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
|
|
MachineInstr *&ADDIMI, int64_t &OffsetAddi,
|
|
int64_t OffsetImm) const;
|
|
|
|
/// Fixup killed/dead flag for register \p RegNo between instructions [\p
|
|
/// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
|
|
/// register killed/dead flags semantics, this function can be called to fix
|
|
/// up. Before calling this function,
|
|
/// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
|
|
/// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
|
|
/// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
|
|
/// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
|
|
/// will be adjust to true definition.
|
|
/// 3. We can do accurate fixup for the case when all instructions between
|
|
/// [\p StartMI, \p EndMI] are in same basic block.
|
|
/// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
|
|
/// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
|
|
/// and for post-RA, we give an assertion as without reaching definition
|
|
/// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
|
|
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
|
|
unsigned RegNo) const;
|
|
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
|
|
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
|
|
int64_t Imm) const;
|
|
|
|
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
|
|
bool PostRA) const;
|
|
|
|
// In PostRA phase, try to find instruction defines \p Reg before \p MI.
|
|
// \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
|
|
MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
|
|
bool &SeenIntermediateUse) const;
|
|
|
|
/// getRegNumForOperand - some operands use different numbering schemes
|
|
/// for the same registers. For example, a VSX instruction may have any of
|
|
/// vs0-vs63 allocated whereas an Altivec instruction could only have
|
|
/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
|
|
/// register number needed for the opcode/operand number combination.
|
|
/// The operand number argument will be useful when we need to extend this
|
|
/// to instructions that use both Altivec and VSX numbering (for different
|
|
/// operands).
|
|
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
|
|
unsigned OpNo) {
|
|
int16_t regClass = Desc.OpInfo[OpNo].RegClass;
|
|
switch (regClass) {
|
|
// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
|
|
// VSX32-VSX63 during encoding/disassembling
|
|
case PPC::VSSRCRegClassID:
|
|
case PPC::VSFRCRegClassID:
|
|
if (isVFRegister(Reg))
|
|
return PPC::VSX32 + (Reg - PPC::VF0);
|
|
break;
|
|
// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
|
|
// VSX32-VSX63 during encoding/disassembling
|
|
case PPC::VSRCRegClassID:
|
|
if (isVRRegister(Reg))
|
|
return PPC::VSX32 + (Reg - PPC::V0);
|
|
break;
|
|
// Other RegClass doesn't need mapping
|
|
default:
|
|
break;
|
|
}
|
|
return Reg;
|
|
}
|
|
|
|
/// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
|
|
bool isBDNZ(unsigned Opcode) const;
|
|
|
|
/// Find the hardware loop instruction used to set-up the specified loop.
|
|
/// On PPC, we have two instructions used to set-up the hardware loop
|
|
/// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
|
|
/// instructions to indicate the end of a loop.
|
|
MachineInstr *
|
|
findLoopInstr(MachineBasicBlock &PreHeader,
|
|
SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
|
|
|
|
/// Analyze loop L, which must be a single-basic-block loop, and if the
|
|
/// conditions can be understood enough produce a PipelinerLoopInfo object.
|
|
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
|
|
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|