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0b6855273a
Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
65 lines
2.0 KiB
Plaintext
65 lines
2.0 KiB
Plaintext
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
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# VI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]
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0x06 0x00 0x82 0xb0
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# VI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
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0x06 0x00 0x02 0xb1
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# VI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
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0x06 0x00 0x82 0xb1
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# VI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
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0x06 0x00 0x02 0xb2
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# VI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
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0x06 0x00 0x82 0xb2
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# VI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
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0x06 0x00 0x02 0xb3
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# VI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
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0x06 0x00 0x82 0xb3
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# VI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
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0x06 0x00 0x02 0xb4
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# VI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
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0x06 0x00 0x82 0xb4
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# VI: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
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0x06 0x00 0x02 0xb5
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# VI: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
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0x06 0x00 0x82 0xb5
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# VI: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
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0x06 0x00 0x02 0xb6
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# VI: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
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0x06 0x00 0x82 0xb6
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# VI: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
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0x06 0x00 0x02 0xb7
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# VI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
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0x06 0x00 0x82 0xb7
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# VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
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0x06 0x00 0x02 0xb8
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# VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
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0x06 0xf8 0x82 0xb8
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# VI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
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0x33,0xf8,0x82,0xb8
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# VI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
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0x73,0xf0,0x82,0xb8
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# VI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
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0x06 0x00 0x02 0xb9
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# VI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
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0x45 0xf0 0x00 0xba 0xff 0x00 0x00 0x00
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