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40a1bbcfdf
Summary:
Most CPUs implementing AES fusion require instruction pairs of the form
AESE Vn, _
AESMC Vn, Vn
and
AESD Vn, _
AESIMC Vn, Vn
The constraint is added to AES(I)MC instructions which use the result of
an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which
constraint source and destination registers to be the same.
A nice side effect of this change is that now all possible pairs are
scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll
test case.
I had to update aes_load_store. The version I added initially was very
reduced and with the new constraint, AESE/AESMC could not be scheduled
back-to-back. I updated the test to be more realistic and still expose
the same scheduling problem as the initial test case.
Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga
Reviewed By: t.p.northover, evandro
Subscribers: aemerson, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35299
llvm-svn: 309495
68 lines
2.8 KiB
ArmAsm
68 lines
2.8 KiB
ArmAsm
; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -show-encoding -output-asm-variant=1 < %s | FileCheck %s
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; RUN: llvm-mc -triple arm64-apple-darwin -mattr='+crypto,+fuse-aes' -show-encoding -output-asm-variant=1 < %s | FileCheck %s
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foo:
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aese.16b v0, v1
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aesd.16b v0, v1
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aesmc.16b v0, v1
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aesimc.16b v0, v1
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sha1c.4s q0, s1, v2
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sha1p.4s q0, s1, v2
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sha1m.4s q0, s1, v2
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sha1su0.4s v0, v1, v2
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sha256h.4s q0, q1, v2
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sha256h2.4s q0, q1, v2
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sha256su1.4s v0, v1, v2
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sha1h s0, s1
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sha1su1.4s v0, v1
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sha256su0.4s v0, v1
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; CHECK: aese.16b v0, v1 ; encoding: [0x20,0x48,0x28,0x4e]
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; CHECK: aesd.16b v0, v1 ; encoding: [0x20,0x58,0x28,0x4e]
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; CHECK: aesmc.16b v0, v1 ; encoding: [0x20,0x68,0x28,0x4e]
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; CHECK: aesimc.16b v0, v1 ; encoding: [0x20,0x78,0x28,0x4e]
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; CHECK: sha1c.4s q0, s1, v2 ; encoding: [0x20,0x00,0x02,0x5e]
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; CHECK: sha1p.4s q0, s1, v2 ; encoding: [0x20,0x10,0x02,0x5e]
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; CHECK: sha1m.4s q0, s1, v2 ; encoding: [0x20,0x20,0x02,0x5e]
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; CHECK: sha1su0.4s v0, v1, v2 ; encoding: [0x20,0x30,0x02,0x5e]
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; CHECK: sha256h.4s q0, q1, v2 ; encoding: [0x20,0x40,0x02,0x5e]
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; CHECK: sha256h2.4s q0, q1, v2 ; encoding: [0x20,0x50,0x02,0x5e]
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; CHECK: sha256su1.4s v0, v1, v2 ; encoding: [0x20,0x60,0x02,0x5e]
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; CHECK: sha1h s0, s1 ; encoding: [0x20,0x08,0x28,0x5e]
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; CHECK: sha1su1.4s v0, v1 ; encoding: [0x20,0x18,0x28,0x5e]
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; CHECK: sha256su0.4s v0, v1 ; encoding: [0x20,0x28,0x28,0x5e]
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aese v2.16b, v3.16b
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aesd v5.16b, v7.16b
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aesmc v11.16b, v13.16b
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aesimc v17.16b, v19.16b
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; CHECK: aese.16b v2, v3 ; encoding: [0x62,0x48,0x28,0x4e]
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; CHECK: aesd.16b v5, v7 ; encoding: [0xe5,0x58,0x28,0x4e]
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; CHECK: aesmc.16b v11, v13 ; encoding: [0xab,0x69,0x28,0x4e]
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; CHECK: aesimc.16b v17, v19 ; encoding: [0x71,0x7a,0x28,0x4e]
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sha1c q23, s29, v3.4s
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sha1p q14, s15, v9.4s
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sha1m q2, s6, v5.4s
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sha1su0 v3.4s, v5.4s, v9.4s
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sha256h q2, q7, v18.4s
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sha256h2 q28, q18, v28.4s
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sha256su1 v4.4s, v5.4s, v9.4s
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sha1h s30, s0
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sha1su1 v10.4s, v21.4s
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sha256su0 v2.4s, v31.4s
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; CHECK: sha1c.4s q23, s29, v3 ; encoding: [0xb7,0x03,0x03,0x5e]
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; CHECK: sha1p.4s q14, s15, v9 ; encoding: [0xee,0x11,0x09,0x5e]
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; CHECK: sha1m.4s q2, s6, v5 ; encoding: [0xc2,0x20,0x05,0x5e]
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; CHECK: sha1su0.4s v3, v5, v9 ; encoding: [0xa3,0x30,0x09,0x5e]
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; CHECK: sha256h.4s q2, q7, v18 ; encoding: [0xe2,0x40,0x12,0x5e]
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; CHECK: sha256h2.4s q28, q18, v28 ; encoding: [0x5c,0x52,0x1c,0x5e]
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; CHECK: sha256su1.4s v4, v5, v9 ; encoding: [0xa4,0x60,0x09,0x5e]
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; CHECK: sha1h s30, s0 ; encoding: [0x1e,0x08,0x28,0x5e]
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; CHECK: sha1su1.4s v10, v21 ; encoding: [0xaa,0x1a,0x28,0x5e]
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; CHECK: sha256su0.4s v2, v31 ; encoding: [0xe2,0x2b,0x28,0x5e]
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