Oliver Stannard cd482a4c4e [ARM] Honor FeatureD16 in the assembler and disassembler ... Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341		2014-11-05 12:06:39 +00:00
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AArch64	[AArch64] Add support for the .inst directive.	2014-10-22 20:35:57 +00:00
ARM	[ARM] Honor FeatureD16 in the assembler and disassembler	2014-11-05 12:06:39 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF	MC, COFF: Make bigobj test compatible with python3	2014-10-14 22:35:11 +00:00
Disassembler	[ARM] Honor FeatureD16 in the assembler and disassembler	2014-11-05 12:06:39 +00:00
ELF	Add back commits r219835 and a fixed version of r219829.	2014-10-17 01:48:58 +00:00
MachO	Don't produce relocations for a difference in a section with no symbols.	2014-11-04 22:10:33 +00:00
Markup
Mips	Revert "[mips] Add names and tests for the hardware registers"	2014-11-04 22:15:05 +00:00
PowerPC	[PPC64] VSX indexed-form loads use wrong instruction format	2014-10-09 17:51:35 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
X86	Don't produce relocations for a difference in a section with no symbols.	2014-11-04 22:10:33 +00:00