mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
ee0d5cd952
This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195
32 lines
1.2 KiB
LLVM
32 lines
1.2 KiB
LLVM
; Test vector multiply-and-add on z14.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
|
|
|
|
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
|
|
|
|
; Test a v4f32 multiply-and-add.
|
|
define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
|
|
<4 x float> %val2, <4 x float> %val3) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: vfmasb %v24, %v26, %v28, %v30
|
|
; CHECK: br %r14
|
|
%ret = call <4 x float> @llvm.fma.v4f32 (<4 x float> %val1,
|
|
<4 x float> %val2,
|
|
<4 x float> %val3)
|
|
ret <4 x float> %ret
|
|
}
|
|
|
|
; Test a v4f32 multiply-and-subtract.
|
|
define <4 x float> @f2(<4 x float> %dummy, <4 x float> %val1,
|
|
<4 x float> %val2, <4 x float> %val3) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK: vfmssb %v24, %v26, %v28, %v30
|
|
; CHECK: br %r14
|
|
%negval3 = fsub <4 x float> <float -0.0, float -0.0,
|
|
float -0.0, float -0.0>, %val3
|
|
%ret = call <4 x float> @llvm.fma.v4f32 (<4 x float> %val1,
|
|
<4 x float> %val2,
|
|
<4 x float> %negval3)
|
|
ret <4 x float> %ret
|
|
}
|