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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
llvm-mirror/test/CodeGen
Matt Arsenault cd69621a21 AMDGPU: More bits of frame index are known to be zero
The maximum private allocation for the whole GPU is 4G,
so the maximum possible index for a single workitem is the
maximum size divided by the smallest granularity for a dispatch.

This increases the number of known zero high bits, which
enables more offset folding. The maximum private size per
workitem with this is 128M but may be smaller still.

llvm-svn: 262153
2016-02-27 20:26:57 +00:00
..
AArch64 Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause assertion failure on AArch64. 2016-02-26 23:25:30 +00:00
AMDGPU AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
ARM
BPF
CPP
Generic Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86. 2016-02-25 00:12:18 +00:00
Hexagon Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Inputs
Mips
MIR
MSP430 MSP430InstrInfo::loadRegFromStackSlot forgets to set register def. 2016-02-24 15:15:02 +00:00
NVPTX
PowerPC [PPC] Legalize FNEG on PPC when possible 2016-02-26 21:59:44 +00:00
SPARC Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
SystemZ
Thumb Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Thumb2
WebAssembly Revert "[WebAssembly] Stackify code emitted by eliminateFrameIndex" 2016-02-23 22:13:21 +00:00
WinEH [WinEH] Don't remove unannotated inline-asm calls 2016-02-26 00:04:25 +00:00
X86 DAGCombiner: Don't unnecessarily swap operands in ReassociateOps 2016-02-27 19:57:45 +00:00
XCore