mirror of
https://github.com/RPCS3/llvm-mirror.git
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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
440 lines
9.2 KiB
LLVM
440 lines
9.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-enable-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s
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;
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; Test folding of the sign-/zero-extend into the load instruction.
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;
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; Unscaled
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define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i32
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; CHECK: ldurb w0, [x0, #-8]
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; CHECK-NOT: uxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i32
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; CHECK: ldurh w0, [x0, #-8]
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; CHECK-NOT: uxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i8_to_i64
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; CHECK: ldurb w0, [x0, #-8]
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; CHECK-NOT: uxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i16_to_i64
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; CHECK: ldurh w0, [x0, #-8]
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; CHECK-NOT: uxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_zext_i32_to_i64
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; CHECK: ldur w0, [x0, #-8]
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; CHECK-NOT: uxtw
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32, i32* %2
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br label %bb2
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bb2:
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%4 = zext i32 %3 to i64
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ret i64 %4
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}
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define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i32
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; CHECK: ldursb w0, [x0, #-8]
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; CHECK-NOT: sxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = sext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i32
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; CHECK: ldursh w0, [x0, #-8]
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; CHECK-NOT: sxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = sext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i8_to_i64
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; CHECK: ldursb x0, [x0, #-8]
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; CHECK-NOT: sxtb
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = sext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i16_to_i64
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; CHECK: ldursh x0, [x0, #-8]
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; CHECK-NOT: sxth
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = sext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
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; CHECK-LABEL: load_unscaled_sext_i32_to_i64
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; CHECK: ldursw x0, [x0, #-8]
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; CHECK-NOT: sxtw
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%1 = sub i64 %a, 8
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32, i32* %2
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br label %bb2
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bb2:
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%4 = sext i32 %3 to i64
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ret i64 %4
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}
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; Register
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define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_zext_i8_to_i32
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; CHECK: ldrb w0, [x0, x1]
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; CHECK-NOT: uxtb
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_zext_i16_to_i32
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; CHECK: ldrh w0, [x0, x1]
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; CHECK-NOT: uxth
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_zext_i8_to_i64
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; CHECK: ldrb w0, [x0, x1]
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; CHECK-NOT: uxtb
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = zext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_zext_i16_to_i64
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; CHECK: ldrh w0, [x0, x1]
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; CHECK-NOT: uxth
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = zext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_zext_i32_to_i64
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; CHECK: ldr w0, [x0, x1]
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; CHECK-NOT: uxtw
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32, i32* %2
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br label %bb2
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bb2:
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%4 = zext i32 %3 to i64
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ret i64 %4
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}
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define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_sext_i8_to_i32
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; CHECK: ldrsb w0, [x0, x1]
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; CHECK-NOT: sxtb
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = sext i8 %3 to i32
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ret i32 %4
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}
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define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_sext_i16_to_i32
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; CHECK: ldrsh w0, [x0, x1]
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; CHECK-NOT: sxth
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = sext i16 %3 to i32
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ret i32 %4
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}
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define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_sext_i8_to_i64
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; CHECK: ldrsb x0, [x0, x1]
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; CHECK-NOT: sxtb
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i8*
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%3 = load i8, i8* %2
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br label %bb2
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bb2:
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%4 = sext i8 %3 to i64
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ret i64 %4
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}
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define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_sext_i16_to_i64
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; CHECK: ldrsh x0, [x0, x1]
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; CHECK-NOT: sxth
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i16*
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%3 = load i16, i16* %2
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br label %bb2
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bb2:
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%4 = sext i16 %3 to i64
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ret i64 %4
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}
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define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: load_register_sext_i32_to_i64
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; CHECK: ldrsw x0, [x0, x1]
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; CHECK-NOT: sxtw
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32, i32* %2
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br label %bb2
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bb2:
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%4 = sext i32 %3 to i64
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ret i64 %4
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}
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; Extend
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define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_zext_i8_to_i32
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; CHECK: ldrb w0, [x0, w1, sxtw]
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; CHECK-NOT: uxtb
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i8*
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%4 = load i8, i8* %3
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br label %bb2
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bb2:
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%5 = zext i8 %4 to i32
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ret i32 %5
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}
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define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_zext_i16_to_i32
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; CHECK: ldrh w0, [x0, w1, sxtw]
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; CHECK-NOT: uxth
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i16*
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%4 = load i16, i16* %3
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br label %bb2
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bb2:
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%5 = zext i16 %4 to i32
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ret i32 %5
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}
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define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_zext_i8_to_i64
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; CHECK: ldrb w0, [x0, w1, sxtw]
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; CHECK-NOT: uxtb
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i8*
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%4 = load i8, i8* %3
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br label %bb2
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bb2:
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%5 = zext i8 %4 to i64
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ret i64 %5
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}
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define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_zext_i16_to_i64
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; CHECK: ldrh w0, [x0, w1, sxtw]
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; CHECK-NOT: uxth
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i16*
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%4 = load i16, i16* %3
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br label %bb2
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bb2:
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%5 = zext i16 %4 to i64
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ret i64 %5
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}
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define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_zext_i32_to_i64
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; CHECK: ldr w0, [x0, w1, sxtw]
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; CHECK-NOT: uxtw
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i32*
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%4 = load i32, i32* %3
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br label %bb2
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bb2:
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%5 = zext i32 %4 to i64
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ret i64 %5
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}
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define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_sext_i8_to_i32
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; CHECK: ldrsb w0, [x0, w1, sxtw]
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; CHECK-NOT: sxtb
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i8*
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%4 = load i8, i8* %3
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br label %bb2
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bb2:
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%5 = sext i8 %4 to i32
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ret i32 %5
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}
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define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_sext_i16_to_i32
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; CHECK: ldrsh w0, [x0, w1, sxtw]
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; CHECK-NOT: sxth
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i16*
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%4 = load i16, i16* %3
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br label %bb2
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bb2:
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%5 = sext i16 %4 to i32
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ret i32 %5
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}
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define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_sext_i8_to_i64
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; CHECK: ldrsb x0, [x0, w1, sxtw]
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; CHECK-NOT: sxtb
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i8*
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%4 = load i8, i8* %3
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br label %bb2
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bb2:
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%5 = sext i8 %4 to i64
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ret i64 %5
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}
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define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_sext_i16_to_i64
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; CHECK: ldrsh x0, [x0, w1, sxtw]
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; CHECK-NOT: sxth
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i16*
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%4 = load i16, i16* %3
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br label %bb2
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bb2:
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%5 = sext i16 %4 to i64
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ret i64 %5
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}
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define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {
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; CHECK-LABEL: load_extend_sext_i32_to_i64
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; CHECK: ldrsw x0, [x0, w1, sxtw]
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; CHECK-NOT: sxtw
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%1 = sext i32 %b to i64
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%2 = add i64 %a, %1
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%3 = inttoptr i64 %2 to i32*
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%4 = load i32, i32* %3
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br label %bb2
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bb2:
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%5 = sext i32 %4 to i64
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ret i64 %5
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}
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