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74f5838ee5
Convert ARMCodeGenPrepare into a generic type promotion pass by: - Removing the insertion of arm specific intrinsics to handle narrow types as we weren't using this. - Removing ARMSubtarget references. - Now query a generic TLI object to know which types should be promoted and what they should be promoted to. - Move all codegen tests into Transforms folder and testing using opt and not llc, which is how they should have been written in the first place... The pass searches up from icmp operands in an attempt to safely promote types so we can avoid generating unnecessary unsigned extends during DAG ISel. Differential Revision: https://reviews.llvm.org/D69556
74 lines
2.6 KiB
C++
74 lines
2.6 KiB
C++
//===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// ARM back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARM_H
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#define LLVM_LIB_TARGET_ARM_ARM_H
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/CodeGen.h"
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#include <functional>
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#include <vector>
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namespace llvm {
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class ARMAsmPrinter;
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class ARMBaseTargetMachine;
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class ARMRegisterBankInfo;
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class ARMSubtarget;
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struct BasicBlockInfo;
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class Function;
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class FunctionPass;
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class InstructionSelector;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MCInst;
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class PassRegistry;
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Pass *createMVETailPredicationPass();
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FunctionPass *createARMLowOverheadLoopsPass();
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Pass *createARMParallelDSPPass();
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createA15SDOptimizerPass();
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createMLxExpansionPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createMVEVPTBlockPass();
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FunctionPass *createARMOptimizeBarriersPass();
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FunctionPass *createThumb2SizeReductionPass(
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std::function<bool(const Function &)> Ftor = nullptr);
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InstructionSelector *
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createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
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const ARMRegisterBankInfo &RBI);
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void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP);
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void initializeARMParallelDSPPass(PassRegistry &);
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void initializeARMLoadStoreOptPass(PassRegistry &);
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void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
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void initializeARMConstantIslandsPass(PassRegistry &);
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void initializeARMExpandPseudoPass(PassRegistry &);
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void initializeThumb2SizeReducePass(PassRegistry &);
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void initializeThumb2ITBlockPass(PassRegistry &);
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void initializeMVEVPTBlockPass(PassRegistry &);
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void initializeARMLowOverheadLoopsPass(PassRegistry &);
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void initializeMVETailPredicationPass(PassRegistry &);
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARM_H
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