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48 lines
1.8 KiB
TableGen
48 lines
1.8 KiB
TableGen
//=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class HexagonV55PseudoItin {
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list<InstrItinData> V55PseudoItin_list = [
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InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
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InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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];
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}
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def HexagonV55ItinList : DepScalarItinV55,
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HexagonV55PseudoItin {
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list<InstrItinData> V55Itin_list = [
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InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
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InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1]>
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];
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list<InstrItinData> ItinList =
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!listconcat(V55Itin_list, DepScalarItinV55_list,
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V55PseudoItin_list);
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}
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def HexagonItinerariesV55 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
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[Hex_FWD], HexagonV55ItinList.ItinList>;
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def HexagonModelV55 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV55;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V55 Resource Definitions -
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//===----------------------------------------------------------------------===//
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