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430 lines
12 KiB
TableGen
430 lines
12 KiB
TableGen
//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the POWER9 processor.
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//
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//===----------------------------------------------------------------------===//
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include "PPCInstrInfo.td"
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def P9Model : SchedMachineModel {
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// The maximum number of instructions to be issued at the same time.
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// While a value of 8 is technically correct since 8 instructions can be
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// fetched from the instruction cache. However, only 6 instructions may be
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// actually dispatched at a time.
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let IssueWidth = 8;
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// Load latency is 4 or 5 cycles depending on the load. This latency assumes
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// that we have a cache hit. For a cache miss the load latency will be more.
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// There are two instructions (lxvl, lxvll) that have a latencty of 6 cycles.
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// However it is not worth bumping this value up to 6 when the vast majority
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// of instructions are 4 or 5 cycles.
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let LoadLatency = 5;
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// A total of 16 cycles to recover from a branch mispredict.
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let MispredictPenalty = 16;
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// Try to make sure we have at least 10 dispatch groups in a loop.
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// A dispatch group is 6 instructions.
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let LoopMicroOpBufferSize = 60;
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// As iops are dispatched to a slice, they are held in an independent slice
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// issue queue until all register sources and other dependencies have been
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// resolved and they can be issued. Each of four execution slices has an
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// 11-entry iop issue queue.
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let MicroOpBufferSize = 44;
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let CompleteModel = 1;
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// Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
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// Engine) on Power 9.
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let UnsupportedFeatures = [HasQPX, HasSPE];
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}
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let SchedModel = P9Model in {
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// ***************** Processor Resources *****************
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// Dispatcher slots:
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// x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each
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// corresponds to one of the four execution slices.
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def DISPx02 : ProcResource<2>;
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def DISPx13 : ProcResource<2>;
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// The xa and xb ports can be used to send an iop to either of the two slices
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// of the superslice, but are restricted to iops with only two primary sources.
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def DISPxab : ProcResource<2>;
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// b0 and b1 are dedicated dispatch ports into the branch slice.
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def DISPb01 : ProcResource<2>;
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// Any non BR dispatch ports
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def DISP_NBR
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: ProcResGroup<[ DISPx02, DISPx13, DISPxab]>;
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def DISP_SS : ProcResGroup<[ DISPx02, DISPx13]>;
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// Issue Ports
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// An instruction can go down one of two issue queues.
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// Address Generation (AGEN) mainly for loads and stores.
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// Execution (EXEC) for most other instructions.
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// Some instructions cannot be run on just any issue queue and may require an
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// Even or an Odd queue. The EXECE represents the even queues and the EXECO
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// represents the odd queues.
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def IP_AGEN : ProcResource<4>;
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def IP_EXEC : ProcResource<4>;
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def IP_EXECE : ProcResource<2> {
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//Even Exec Ports
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let Super = IP_EXEC;
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}
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def IP_EXECO : ProcResource<2> {
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//Odd Exec Ports
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let Super = IP_EXEC;
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}
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// Pipeline Groups
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// Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
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def ALU : ProcResource<4>;
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def ALUE : ProcResource<2> {
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//Even ALU pipelines
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let Super = ALU;
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}
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def ALUO : ProcResource<2> {
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//Odd ALU pipelines
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let Super = ALU;
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}
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// Two DIV (Fixed Point Divide) units.
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def DIV : ProcResource<2>;
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// Four DP (Floating Point) units in total. Two even, two Odd.
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def DP : ProcResource<4>;
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def DPE : ProcResource<2> {
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//Even DP pipelines
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let Super = DP;
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}
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def DPO : ProcResource<2> {
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//Odd DP pipelines
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let Super = DP;
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}
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// Four LS (Load or Store) units.
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def LS : ProcResource<4>;
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// Two PM (Permute) units.
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def PM : ProcResource<2>;
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// Only one DFU (Decimal Floating Point and Quad Precision) unit.
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def DFU : ProcResource<1>;
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// Only one Branch unit.
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def BR : ProcResource<1> {
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let BufferSize = 16;
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}
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// Only one CY (Crypto) unit.
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def CY : ProcResource<1>;
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// ***************** SchedWriteRes Definitions *****************
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// Dispatcher
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// Dispatch Rules: '-' or 'V'
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// Vector ('V') - vector iops (128-bit operand) take only one decode and
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// dispatch slot but are dispatched to both the even and odd slices of a
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// superslice.
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def DISP_1C : SchedWriteRes<[DISP_NBR]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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// Dispatch Rules: 'E'
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// Even slice ('E')- certain operations must be sent only to an even slice.
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// Also consumes odd dispatch slice slot of the same superslice at dispatch
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def DISP_EVEN_1C : SchedWriteRes<[ DISPx02, DISPx13 ]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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// Dispatch Rules: 'P'
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// Paired ('P') - certain cracked and expanded iops are paired such that they
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// must dispatch together to the same superslice.
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def DISP_PAIR_1C : SchedWriteRes<[ DISP_SS, DISP_SS]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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// Tuple Restricted ('R') - certain iops preclude dispatching more than one
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// operation per slice for the super- slice to which they are dispatched
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def DISP_3SLOTS_1C : SchedWriteRes<[DISPx02, DISPx13, DISPxab]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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// Each execution and branch slice can receive up to two iops per cycle
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def DISP_BR_1C : SchedWriteRes<[ DISPxab ]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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// Issue Ports
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def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
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let NumMicroOps = 0;
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let Latency = 1;
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}
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//Pipeline Groups
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// ALU Units
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// An ALU may take either 2 or 3 cycles to complete the operation.
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// However, the ALU unit is only ever busy for 1 cycle at a time and may
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// receive new instructions each cycle.
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def P9_ALU_2C : SchedWriteRes<[ALU]> {
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let Latency = 2;
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}
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def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
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let Latency = 2;
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}
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def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
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let Latency = 2;
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}
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def P9_ALU_3C : SchedWriteRes<[ALU]> {
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let Latency = 3;
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}
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def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
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let Latency = 3;
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}
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def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
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let Latency = 3;
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}
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// DIV Unit
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// A DIV unit may take from 5 to 40 cycles to complete.
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// Some DIV operations may keep the unit busy for up to 8 cycles.
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def P9_DIV_5C : SchedWriteRes<[DIV]> {
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let Latency = 5;
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}
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def P9_DIV_12C : SchedWriteRes<[DIV]> {
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let Latency = 12;
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}
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def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
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let ResourceCycles = [8];
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let Latency = 16;
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}
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def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
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let ResourceCycles = [8];
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let Latency = 24;
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}
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def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
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let ResourceCycles = [8];
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let Latency = 40;
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}
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// DP Unit
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// A DP unit may take from 2 to 36 cycles to complete.
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// Some DP operations keep the unit busy for up to 10 cycles.
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def P9_DP_5C : SchedWriteRes<[DP]> {
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let Latency = 5;
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}
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def P9_DP_7C : SchedWriteRes<[DP]> {
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let Latency = 7;
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}
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def P9_DPE_7C : SchedWriteRes<[DPE]> {
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let Latency = 7;
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}
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def P9_DPO_7C : SchedWriteRes<[DPO]> {
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let Latency = 7;
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}
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def P9_DP_22C_5 : SchedWriteRes<[DP]> {
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let ResourceCycles = [5];
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let Latency = 22;
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}
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def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
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let ResourceCycles = [8];
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let Latency = 24;
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}
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def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
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let ResourceCycles = [8];
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let Latency = 24;
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}
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def P9_DP_26C_5 : SchedWriteRes<[DP]> {
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let ResourceCycles = [5];
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let Latency = 22;
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}
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def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
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let ResourceCycles = [10];
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let Latency = 27;
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}
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def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
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let ResourceCycles = [10];
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let Latency = 27;
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}
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def P9_DP_33C_8 : SchedWriteRes<[DP]> {
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let ResourceCycles = [8];
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let Latency = 33;
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}
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def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
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let ResourceCycles = [8];
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let Latency = 33;
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}
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def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
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let ResourceCycles = [8];
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let Latency = 33;
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}
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def P9_DP_36C_10 : SchedWriteRes<[DP]> {
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let ResourceCycles = [10];
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let Latency = 36;
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}
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def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
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let ResourceCycles = [10];
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let Latency = 36;
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}
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def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
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let ResourceCycles = [10];
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let Latency = 36;
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}
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// PM Unit
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// Three cycle permute operations.
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def P9_PM_3C : SchedWriteRes<[PM]> {
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let Latency = 3;
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}
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// Load and Store Units
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// Loads can have 4, 5 or 6 cycles of latency.
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// Stores are listed as having a single cycle of latency. This is not
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// completely accurate since it takes more than 1 cycle to actually store
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// the value. However, since the store does not produce a result it can be
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// considered complete after one cycle.
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def P9_LS_1C : SchedWriteRes<[LS]> {
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let Latency = 1;
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}
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def P9_LS_4C : SchedWriteRes<[LS]> {
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let Latency = 4;
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}
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def P9_LS_5C : SchedWriteRes<[LS]> {
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let Latency = 5;
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}
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def P9_LS_6C : SchedWriteRes<[LS]> {
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let Latency = 6;
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}
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// DFU Unit
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// Some of the most expensive ops use the DFU.
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// Can take from 12 cycles to 76 cycles to obtain a result.
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// The unit may be busy for up to 62 cycles.
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def P9_DFU_12C : SchedWriteRes<[DFU]> {
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let Latency = 12;
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}
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def P9_DFU_23C : SchedWriteRes<[DFU]> {
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let Latency = 23;
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let ResourceCycles = [11];
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}
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def P9_DFU_24C : SchedWriteRes<[DFU]> {
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let Latency = 24;
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let ResourceCycles = [12];
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}
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def P9_DFU_37C : SchedWriteRes<[DFU]> {
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let Latency = 37;
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let ResourceCycles = [25];
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}
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def P9_DFU_58C : SchedWriteRes<[DFU]> {
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let Latency = 58;
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let ResourceCycles = [44];
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}
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def P9_DFU_76C : SchedWriteRes<[DFU]> {
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let Latency = 76;
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let ResourceCycles = [62];
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}
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// 2 or 5 cycle latencies for the branch unit.
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def P9_BR_2C : SchedWriteRes<[BR]> {
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let Latency = 2;
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}
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def P9_BR_5C : SchedWriteRes<[BR]> {
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let Latency = 5;
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}
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// 6 cycle latency for the crypto unit
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def P9_CY_6C : SchedWriteRes<[CY]> {
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let Latency = 6;
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}
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// ***************** WriteSeq Definitions *****************
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// These are combinations of the resources listed above.
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// The idea is that some cracked instructions cannot be done in parallel and
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// so the latencies for their resources must be added.
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def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
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def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
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def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
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def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
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def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
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def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
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def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
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def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
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def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
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def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
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def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
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def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
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def P9_ALUOpAndALUOpAndALUOp_6C :
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WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
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def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
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def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
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def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
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def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>;
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def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
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def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>;
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def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
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// Include the resource requirements of individual instructions.
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include "P9InstrResources.td"
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}
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