Sjoerd Meijer cda6f69edf [AArch64] Cost-model i8 vector loads/stores ... Loads of <4 x i8> vectors were modeled as extremely expensive. And while we don't have a load instruction that supports this, it isn't that expensive to create a vector of i8 elements. The codegen for this was fixed/optimised in D105110. This now tweaks the cost model and enables SLP vectorisation of my motivating case loadi8.ll. Differential Revision: https://reviews.llvm.org/D103629		2021-07-05 11:25:10 +01:00
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AArch64	[AArch64] Cost-model i8 vector loads/stores	2021-07-05 11:25:10 +01:00
AMDGPU	[AMDGPU] PHI node cost should not be counted for the size and latency.	2021-06-30 16:11:17 +03:00
ARM	[InstructionCost] Don't conflate Invalid costs with Unknown costs.	2021-03-30 09:29:42 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
SystemZ	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
X86	[CostModel][X86] Drop some hard coded fp<->int scalarization costs	2021-07-02 14:29:32 +01:00
free-intrinsics-datalayout.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
free-intrinsics-no_info.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
no_info.ll