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llvm-mirror/test/CodeGen
Alex Lorenz cddac3ca8f MIR Serialization: Serialize the sub register indices.
This commit serializes the sub register indices from the register machine
operands.

Reviewers: Duncan P. N. Exon Smith
llvm-svn: 242084
2015-07-13 23:24:34 +00:00
..
AArch64 [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks. 2015-07-10 22:09:55 +00:00
AMDGPU AMDGPU/SI: Select mad patterns to v_mac_f32 2015-07-13 15:47:57 +00:00
ARM ARM: Fix cttz expansion on vector types. 2015-07-13 15:37:30 +00:00
BPF
CPP
Generic llc: Add a 'run-pass' option. 2015-07-06 17:44:26 +00:00
Hexagon [Hexagon] Add support for atomic RMW operations 2015-07-09 14:51:21 +00:00
Inputs
Mips
MIR MIR Serialization: Serialize the sub register indices. 2015-07-13 23:24:34 +00:00
MSP430
NVPTX Actually support volatile memcpys in NVPTX lowering 2015-07-10 15:40:33 +00:00
PowerPC [PPC64LE] More improvements to VSX swap optimization 2015-07-13 22:58:19 +00:00
SPARC [SPARC] Cleanup handling of the Y/ASR registers. 2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-10 18:28:49 +00:00
WebAssembly [WebAssembly] Create a CodeGen unittest directory. 2015-07-06 23:14:57 +00:00
WinEH [WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name 2015-07-13 17:55:14 +00:00
X86 [WinEH] Emit the LSDA even if no lpads remain but outlining occurred 2015-07-13 20:41:46 +00:00
XCore