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On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. However, the default register class for 32-bit integers is GRX32, which also contains the high 32-bit part registers. In order to never end up with a case of such a COPY into a high reg, this patch adds a new simple pre-RA pass that selects such COPYs into target instructions. This pass also handles COPYs from CC (Condition Code register), and COPYs to CC can now also be emitted from a high reg in copyPhysReg(). Fixes: https://bugs.llvm.org/show_bug.cgi?id=44254 Review: Ulrich Weigand. Differential Revision: https://reviews.llvm.org/D75014
121 lines
3.8 KiB
C++
121 lines
3.8 KiB
C++
//===---------- SystemZPhysRegCopy.cpp - Handle phys reg copies -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass makes sure that a COPY of a physical register will be
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// implementable after register allocation in copyPhysReg() (this could be
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// done in EmitInstrWithCustomInserter() instead if COPY instructions would
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// be passed to it).
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define SYSTEMZ_COPYPHYSREGS_NAME "SystemZ Copy Physregs"
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namespace llvm {
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void initializeSystemZCopyPhysRegsPass(PassRegistry&);
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}
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namespace {
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class SystemZCopyPhysRegs : public MachineFunctionPass {
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public:
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static char ID;
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SystemZCopyPhysRegs()
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: MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
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initializeSystemZCopyPhysRegsPass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override { return SYSTEMZ_COPYPHYSREGS_NAME; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool visitMBB(MachineBasicBlock &MBB);
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const SystemZInstrInfo *TII;
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MachineRegisterInfo *MRI;
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};
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char SystemZCopyPhysRegs::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(SystemZCopyPhysRegs, "systemz-copy-physregs",
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SYSTEMZ_COPYPHYSREGS_NAME, false, false)
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FunctionPass *llvm::createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM) {
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return new SystemZCopyPhysRegs();
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}
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void SystemZCopyPhysRegs::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool SystemZCopyPhysRegs::visitMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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// Certain special registers can only be copied from a subset of the
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// default register class of the type. It is therefore necessary to create
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// the target copy instructions before regalloc instead of in copyPhysReg().
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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MBBI != E; ) {
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MachineInstr *MI = &*MBBI++;
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if (!MI->isCopy())
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continue;
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DebugLoc DL = MI->getDebugLoc();
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Register SrcReg = MI->getOperand(1).getReg();
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Register DstReg = MI->getOperand(0).getReg();
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if (DstReg.isVirtual() &&
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(SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
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Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
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if (SrcReg == SystemZ::CC)
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BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp);
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else
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BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
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MI->getOperand(1).setReg(Tmp);
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Modified = true;
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}
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else if (SrcReg.isVirtual() &&
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SystemZ::AR32BitRegClass.contains(DstReg)) {
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Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
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MI->getOperand(0).setReg(Tmp);
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BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
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Modified = true;
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}
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}
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return Modified;
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}
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bool SystemZCopyPhysRegs::runOnMachineFunction(MachineFunction &F) {
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TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
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MRI = &F.getRegInfo();
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bool Modified = false;
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for (auto &MBB : F)
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Modified |= visitMBB(MBB);
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return Modified;
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}
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