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fb51a50eef
More or less all the instructions defined in the v8.2a full-fp16 extension are defined as UNPREDICTABLE if you put them in an IT block (Thumb) or use with any condition other than AL (ARM). LLVM didn't know that, and was happy to conditionalise them. In order to force these instructions to count as not predicable, I had to make a small Tablegen change. The code generation back end mostly decides if an instruction was predicable by looking for something it can identify as a predicate operand; there's an isPredicable bit flag that overrides that check in the positive direction, but nothing that overrides it in the negative direction. (I considered the alternative approach of actually removing the predicate operand from those instructions, but thought that it would be more painful overall for instructions differing only in data type to have different shapes of operand list. This way, the only code that has to notice the difference is the if-converter.) So I've added an isUnpredicable bit alongside isPredicable, and set that bit on the right subset of FP16 instructions, and also on the VSEL, VMAXNM/VMINNM and VRINT[ANPM] families which should be unpredicable for all data types. I've included a couple of representative regression tests, both of which previously caused an fp16 instruction to be conditionalised in ARM state and (with -arm-no-restrict-it) to be put in an IT block in Thumb. Reviewers: SjoerdMeijer, t.p.northover, efriedma Reviewed By: efriedma Subscribers: jdoerfert, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57823 llvm-svn: 354768
114 lines
3.4 KiB
ArmAsm
114 lines
3.4 KiB
ArmAsm
@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
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@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -arm-implicit-it always < %s 2>&1 | FileCheck %s
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vaddeq.f16 s0, s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vsubne.f16 s0, s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vdivmi.f16 s0, s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmulpl.f16 s0, s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vnmulvs.f16 s0, s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmlavc.f16 s1, s2, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmlshs.f16 s1, s2, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vnmlalo.f16 s1, s2, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vnmlscs.f16 s1, s2, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcmpcc.f16 s0, s1
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcmphi.f16 s2, #0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcmpels.f16 s1, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcmpege.f16 s0, #0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vabslt.f16 s0, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vneggt.f16 s0, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vsqrtle.f16 s0, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcvteq.f16.s32 s0, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcvtne.u32.f16 s0, s0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vcvtrmi.s32.f16 s0, s1
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vrintzhs.f16 s3, s24
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vrintrlo.f16 s0, s9
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vrintxcs.f16 s10, s14
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vfmalt.f16 s2, s7, s4
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vfmsgt.f16 s2, s7, s4
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vfnmale.f16 s2, s7, s4
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vfnmseq.f16 s2, s7, s4
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vldrpl.16 s1, [pc, #6]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vldrvs.16 s2, [pc, #510]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vldrvc.16 s3, [pc, #-510]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vldrhs.16 s4, [r4, #-18]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vstrlo.16 s1, [pc, #6]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vstrcs.16 s2, [pc, #510]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vstrcc.16 s3, [pc, #-510]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vstrhi.16 s4, [r4, #-18]
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmovls.f16 s0, #1.0
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmovge.f16 s1, r2
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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vmovlt.f16 r3, s4
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@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
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