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llvm-mirror/test/CodeGen/AMDGPU
Matt Arsenault 6a84ed648e GlobalISel: Do not change register types in lowerLoad
Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.

For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.
2021-05-27 11:49:37 -04:00
..
GlobalISel GlobalISel: Do not change register types in lowerLoad 2021-05-27 11:49:37 -04:00
32-bit-local-address-space.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
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llvm.amdgcn.atomic.dec.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
llvm.amdgcn.atomic.fadd.gfx90a.ll
llvm.amdgcn.atomic.fadd.ll
llvm.amdgcn.atomic.inc.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
llvm.amdgcn.ballot.i32.ll
llvm.amdgcn.ballot.i64.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.dwordx3.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.append.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
llvm.amdgcn.ds.gws.barrier.ll
llvm.amdgcn.ds.gws.init.ll
llvm.amdgcn.ds.gws.sema.br.ll
llvm.amdgcn.ds.gws.sema.p.ll
llvm.amdgcn.ds.gws.sema.release.all.ll
llvm.amdgcn.ds.gws.sema.v.ll
llvm.amdgcn.ds.ordered.add.gfx10.ll
llvm.amdgcn.ds.ordered.add.ll
llvm.amdgcn.ds.ordered.swap.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fma.legacy.ll
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll
llvm.amdgcn.image.a16.encode.ll
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.gfx90a.ll
llvm.amdgcn.image.dim.ll
llvm.amdgcn.image.gather4.a16.dim.ll
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll
llvm.amdgcn.image.gather4.o.dim.ll
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll
llvm.amdgcn.image.load.a16.ll
llvm.amdgcn.image.msaa.load.x.ll
llvm.amdgcn.image.nsa.ll
llvm.amdgcn.image.sample.a16.dim.ll
llvm.amdgcn.image.sample.d16.dim.ll
llvm.amdgcn.image.sample.dim.gfx90a.ll
llvm.amdgcn.image.sample.dim.ll
llvm.amdgcn.image.sample.g16.a16.dim.ll
llvm.amdgcn.image.sample.g16.encode.ll
llvm.amdgcn.image.sample.g16.ll
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll
llvm.amdgcn.image.store.a16.d16.ll
llvm.amdgcn.image.store.a16.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.intersect_ray.ll
llvm.amdgcn.is.private.ll
llvm.amdgcn.is.shared.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.bf16.ll
llvm.amdgcn.mfma.gfx90a.ll
llvm.amdgcn.mfma.i8.ll
llvm.amdgcn.mfma.ll
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.perm.ll
llvm.amdgcn.permlane.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.fadd.ll
llvm.amdgcn.raw.buffer.atomic.ll
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm.amdgcn.raw.tbuffer.load.ll
llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm.amdgcn.raw.tbuffer.store.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
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llvm.amdgcn.rsq.ll
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llvm.amdgcn.s.buffer.load.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
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llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sethalt.ll
llvm.amdgcn.s.setreg.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
llvm.amdgcn.sqrt.f16.ll
llvm.amdgcn.sqrt.ll
llvm.amdgcn.struct.buffer.atomic.fadd.ll
llvm.amdgcn.struct.buffer.atomic.ll
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llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.ll
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
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llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
llvm.amdgcn.workgroup.id.ll
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llvm.cos.f16.ll
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llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
llvm.log10.ll
llvm.log.f16.ll
llvm.log.ll
llvm.maxnum.f16.ll
llvm.memcpy.ll
llvm.minnum.f16.ll
llvm.mulo.ll
llvm.pow-gfx9.ll
llvm.pow.ll
llvm.powi.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
lo16-32bit-physreg-copy.mir
lo16-hi16-illegal-copy.mir
lo16-hi16-physreg-copy.mir
lo16-lo16-physreg-copy-agpr.mir
lo16-lo16-physreg-copy-sgpr.mir
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-local-redundant-copies.ll
load-local.96.ll
load-local.128.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
local-memory.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
local-memory.r600.ll
local-stack-alloc-block-sp-reference.ll
local-stack-slot-offset.ll
loop_break.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
loop_exit_with_xor.ll
loop_header_nopred.mir
loop-address.ll
loop-idiom.ll
loop-live-out-copy-undef-subrange.ll
loop-prefetch.ll
lower-control-flow-other-terminators.mir
lower-kernargs.ll
lower-kernel-and-module-lds.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-kernel-lds-constexpr.ll [AMDGPU] Fix kernel LDS lowering for constants 2021-05-26 11:34:50 -07:00
lower-kernel-lds.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-mem-intrinsics-threshold.ll
lower-mem-intrinsics.ll
lower-module-lds-constantexpr.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-inactive.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-indirect.ll
lower-module-lds-offsets.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-used-list.ll
lower-module-lds.ll
lower-range-metadata-intrinsic-call.ll
lower-term-opcodes.mir
lshl64-to-32.ll
lshr.v2i16.ll
machine-cse-commute-target-flags.mir
machinelicm-convergent.mir
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll
mad-mix.ll
mad.u16.ll
madak-inline-constant.mir
madak.ll
madmk.ll
mai-hazards-gfx90a.mir
mai-hazards.mir
mai-inline.ll
max3.ll
max-literals.ll
max-sgprs.ll
max.i16.ll
max.ll
mcp-overlap-after-propagation.mir
med3-no-simplify.ll
mem-builtins.ll
memcpy-fixed-align.ll
memcpy-inline-fails.ll
memcpy-scoped-aa.ll [SelectionDAG] Propagate scoped AA metadata when lowering mem intrinsics. 2021-05-25 14:42:26 -04:00
memory_clause.ll
memory_clause.mir
memory-legalizer-atomic-insert-end.mir
memory-legalizer-fence.ll
memory-legalizer-flat-agent.ll
memory-legalizer-flat-nontemporal.ll
memory-legalizer-flat-singlethread.ll
memory-legalizer-flat-system.ll
memory-legalizer-flat-volatile.ll
memory-legalizer-flat-wavefront.ll
memory-legalizer-flat-workgroup.ll
memory-legalizer-global-agent.ll
memory-legalizer-global-nontemporal.ll
memory-legalizer-global-singlethread.ll
memory-legalizer-global-system.ll
memory-legalizer-global-volatile.ll
memory-legalizer-global-wavefront.ll
memory-legalizer-global-workgroup.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-local-agent.ll
memory-legalizer-local-nontemporal.ll
memory-legalizer-local-singlethread.ll
memory-legalizer-local-system.ll
memory-legalizer-local-volatile.ll
memory-legalizer-local-wavefront.ll
memory-legalizer-local-workgroup.ll
memory-legalizer-local.mir
memory-legalizer-multiple-mem-operands-atomics.mir
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
memory-legalizer-private-nontemporal.ll
memory-legalizer-private-volatile.ll
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
merge-image-load-gfx10.mir
merge-image-load.mir
merge-image-sample-gfx10.mir
merge-image-sample.mir
merge-load-store-agpr.mir
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir
merge-m0.mir
merge-out-of-order-ldst.ll
merge-out-of-order-ldst.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
merge-tbuffer.mir
mesa3d.ll
mesa_regression.ll
mfma-loop.ll
min3.ll
min.ll
mir-print-dead-csr-fi.mir
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
mixed-wave32-wave64.ll
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-load-addr-to-valu.mir
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
mubuf-legalize-operands.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul24-pass-ordering.ll
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.i16.ll
mul.ll
multi-divergent-exit-region.ll
multi-dword-vgpr-spill.ll
multilevel-break.ll
nand.ll
need-fp-from-csr-vgpr-spill.ll
nested-calls.ll
nested-loop-conditions.ll
no-bundle-asm.ll
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-remat-indirect-mov.mir
no-shrink-extloads.ll
non-entry-alloca.ll
noop-shader-O0.ll
nop-data.ll
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
nsa-reassign.mir
nsa-vmem-hazard.mir
nullptr.ll
occupancy-levels.ll
offset-split-flat.ll
offset-split-global.ll
omod-nsz-flag.mir
omod.ll
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll
operand-folding.ll
operand-spacing.ll
opt_exec_copy_fold.mir
opt-pipeline.ll
opt-sgpr-to-vgpr-copy.mir
optimize-exec-copies-extra-insts-after-copy.mir
optimize-exec-mask-pre-ra-loop-phi.mir
optimize-exec-masking-pre-ra.mir
optimize-exec-masking-strip-terminator-bits.mir
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir
optimize-negated-cond-exec-masking.mir
optimize-negated-cond.ll
or3.ll
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-fp32.ll
packed-op-sel.ll
packetizer.ll
pal-simple-indirect-call.ll [AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv 2021-05-27 10:41:40 +02:00
pal-userdata-regs.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-build-spill-partial-agpr.mir
pei-build-spill.mir
pei-reg-scavenger-position.mir
pei-scavenge-sgpr-carry-out.mir
pei-scavenge-sgpr-gfx9.mir
pei-scavenge-sgpr.mir
pei-scavenge-vgpr-spill.mir
perfhint.ll
permute.ll
phi-elimination-assertion.mir
phi-elimination-end-cf.mir
phi-vgpr-input-moveimm.mir
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir
post-ra-sched-reset.mir
post-ra-soft-clause-dbg-info.ll
postra-bundle-memops.mir
postra-machine-sink.mir
postra-norename.mir
power-sched-no-instr-sunit.mir
predicate-dp4.ll
predicates.ll
preserve-hi16.ll
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
promote-alloca-pointer-array.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-constantexpr-use.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir
promote-constOffset-to-imm-gfx90a.mir
promote-constOffset-to-imm.ll
promote-constOffset-to-imm.mir
promote-vect3-load.ll
propagate-attributes-bitcast-function.ll
propagate-attributes-clone.ll
propagate-attributes-flat-work-group-size.ll
propagate-attributes-function-pointer-argument.ll [AMDGPU] Fix function pointer argument bug in AMDGPU Propagate Attributes pass. 2021-05-26 16:40:15 +02:00
propagate-attributes-single-set.ll
ptr-arg-dbg-value.ll
ptrmask.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
readlane_exec0.mir
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
register-count-comments.ll
rel32.ll
remove-short-exec-branches-gpr-idx-mode.mir
remove-short-exec-branches-special-instructions.mir
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll
reserve-vgpr-for-sgpr-spill.ll
reserved-reg-in-clause.mir
ret_jump.ll
ret.ll
return-with-successors.mir
returnaddress.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
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sched-assert-dead-def-subreg-use-other-subreg.mir
sched-assert-onlydbg-value-empty-region.mir
sched-crash-dbg-value.mir
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sched-prefer-non-mfma.mir
schedule-barrier-fpmode.mir
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sdwa-peephole-instr.mir
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sdwa-preserve.mir
sdwa-scalar-ops.mir
sdwa-stack.mir
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set-dx10.ll
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setcc64.ll
setcc-equivalent.ll
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sgpr-copy-duplicate-operand.ll
sgpr-copy-local-cse.ll
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sgpr-spill-dead-frame-in-dbg-value.mir
sgpr-spill-partially-undef.mir
sgpr-spill-wrong-stack-id.mir
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shift-i128.ll
shift-select.ll
shl_add_constant.ll
shl_add_ptr_csub.ll
shl_add_ptr_global.ll
shl_add_ptr.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
shl_add.ll
shl_or.ll
shl-add-to-add-shl.ll
shl.ll
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shrink-vop3-carry-out.mir
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simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sink-image-sample.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
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skip-branch-trap.ll
skip-if-dead.ll
skip-promote-alloca-vector-users.ll
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smem-war-hazard.mir
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soft-clause-dbg-value.mir
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speculative-execution-freecasts.ll
spill192.mir
spill_more_than_wavesize_csr_sgprs.ll
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spill-agpr.ll
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spill-alloc-sgpr-init-bug.ll
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spill-m0.ll
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sra.ll
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strict_fadd.f16.ll
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tid-mul-func-xnack-all-any.ll
tid-mul-func-xnack-all-not-supported.ll
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tid-one-func-xnack-any.ll
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token-factor-inline-limit-test.ll
transform-block-with-return-to-epilog.ll
trap-abis.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store-i64.ll
trunc-store-vec-i16-to-i8.ll
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unaligned-load-store.ll
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zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.