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317f9a63d2
Instruction combining pass turns library rotl implementation to llvm.fshl.i16. In the selection dag the intrinsic is turned to ISD::ROTL node that cannot be selected. Need to expand it to shifts again. Reviewed By: rampitec, arsenm Differential Revision: https://reviews.llvm.org/D87618
79 lines
2.7 KiB
LLVM
79 lines
2.7 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}rotr_i32:
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; R600: BIT_ALIGN_INT
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; SI: v_alignbit_b32
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define amdgpu_kernel void @rotr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%tmp0 = sub i32 32, %y
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%tmp1 = shl i32 %x, %tmp0
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%tmp2 = lshr i32 %x, %y
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%tmp3 = or i32 %tmp1, %tmp2
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store i32 %tmp3, i32 addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: {{^}}rotr_v2i32:
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; SI: v_alignbit_b32
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; SI: v_alignbit_b32
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define amdgpu_kernel void @rotr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
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entry:
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%tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
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%tmp1 = shl <2 x i32> %x, %tmp0
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%tmp2 = lshr <2 x i32> %x, %y
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%tmp3 = or <2 x i32> %tmp1, %tmp2
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store <2 x i32> %tmp3, <2 x i32> addrspace(1)* %in
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ret void
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}
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; FUNC-LABEL: {{^}}rotr_v4i32:
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; R600: BIT_ALIGN_INT
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; SI: v_alignbit_b32
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; SI: v_alignbit_b32
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; SI: v_alignbit_b32
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; SI: v_alignbit_b32
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define amdgpu_kernel void @rotr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
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entry:
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%tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
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%tmp1 = shl <4 x i32> %x, %tmp0
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%tmp2 = lshr <4 x i32> %x, %y
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%tmp3 = or <4 x i32> %tmp1, %tmp2
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store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %in
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ret void
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}
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; GCN-LABEL: @test_rotr_i16
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; GCN: global_load_ushort [[X:v[0-9]+]]
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; GCN: global_load_ushort [[D:v[0-9]+]]
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; GCN: v_sub_nc_u16_e64 [[NX:v[0-9]+]], 0, [[X]]
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; GCN: v_and_b32_e32 [[XAND:v[0-9]+]], 15, [[X]]
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; GCN: v_and_b32_e32 [[NXAND:v[0-9]+]], 15, [[NX]]
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; GCN: v_lshrrev_b16_e64 [[LO:v[0-9]+]], [[XAND]], [[D]]
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; GCN: v_lshlrev_b16_e64 [[HI:v[0-9]+]], [[NXAND]], [[D]]
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; GCN: v_or_b32_e32 [[RES:v[0-9]+]], [[LO]], [[HI]]
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; GCN: global_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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define void @test_rotr_i16(i16 addrspace(1)* nocapture readonly %sourceA, i16 addrspace(1)* nocapture readonly %sourceB, i16 addrspace(1)* nocapture %destValues) {
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entry:
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%arrayidx = getelementptr inbounds i16, i16 addrspace(1)* %sourceA, i64 16
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%a = load i16, i16 addrspace(1)* %arrayidx
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%arrayidx2 = getelementptr inbounds i16, i16 addrspace(1)* %sourceB, i64 24
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%b = load i16, i16 addrspace(1)* %arrayidx2
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%c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
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%arrayidx5 = getelementptr inbounds i16, i16 addrspace(1)* %destValues, i64 4
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store i16 %c, i16 addrspace(1)* %arrayidx5
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ret void
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}
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