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141 lines
5.1 KiB
LLVM
141 lines
5.1 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s
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; RUN: llc -O0 -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
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; GCN-LABEL: {{^}}zext_grp_size_128:
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; GCN-NOT: and_b32
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; OPT-LABEL: @zext_grp_size_128
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !0
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !0
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define amdgpu_kernel void @zext_grp_size_128(i32 addrspace(1)* nocapture %arg) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = and i32 %tmp, 127
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store i32 %tmp1, i32 addrspace(1)* %arg, align 4
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%tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%tmp3 = and i32 %tmp2, 127
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()
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%tmp6 = and i32 %tmp5, 127
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%tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; GCN-LABEL: {{^}}zext_grp_size_32x4x1:
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; GCN-NOT: and_b32
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; OPT-LABEL: @zext_grp_size_32x4x1
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !2
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !3
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !4
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define amdgpu_kernel void @zext_grp_size_32x4x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = and i32 %tmp, 31
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store i32 %tmp1, i32 addrspace(1)* %arg, align 4
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%tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%tmp3 = and i32 %tmp2, 3
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()
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%tmp6 = and i32 %tmp5, 1
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%tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; GCN-LABEL: {{^}}zext_grp_size_1x1x1:
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; GCN-NOT: and_b32
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; When EarlyCSE is not run this call produces a range max with 0 active bits,
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; which is a special case as an AssertZext from width 0 is invalid.
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; OPT-LABEL: @zext_grp_size_1x1x1
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !4
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define amdgpu_kernel void @zext_grp_size_1x1x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !1 {
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = and i32 %tmp, 1
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store i32 %tmp1, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: {{^}}zext_grp_size_512:
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; GCN-NOT: and_b32
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; OPT-LABEL: @zext_grp_size_512
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !6
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !6
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define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = and i32 %tmp, 65535
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store i32 %tmp1, i32 addrspace(1)* %arg, align 4
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%tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%tmp3 = and i32 %tmp2, 65535
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()
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%tmp6 = and i32 %tmp5, 65535
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%tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4
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ret void
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}
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; GCN-LABEL: {{^}}func_test_workitem_id_x_known_max_range:
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; O2-NOT: and_b32
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; O2: v_and_b32_e32 v{{[0-9]+}}, 0x3ff,
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; O2-NOT: and_b32
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; OPT-LABEL: @func_test_workitem_id_x_known_max_range(
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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define void @func_test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%and = and i32 %id, 1023
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}func_test_workitem_id_x_default_range:
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; O2-NOT: and_b32
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; O2: v_and_b32_e32 v{{[0-9]+}}, 0x3ff,
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; O2-NOT: and_b32
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; OPT-LABEL: @func_test_workitem_id_x_default_range(
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; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !7
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define void @func_test_workitem_id_x_default_range(i32 addrspace(1)* nocapture %out) #4 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%and = and i32 %id, 1023
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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declare i32 @llvm.amdgcn.workitem.id.y() #2
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declare i32 @llvm.amdgcn.workitem.id.z() #2
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attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,128" }
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attributes #1 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
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attributes #2 = { nounwind readnone speculatable }
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attributes #3 = { nounwind readnone }
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attributes #4 = { nounwind }
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!0 = !{i32 32, i32 4, i32 1}
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!1 = !{i32 1, i32 1, i32 1}
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; OPT: !0 = !{i32 0, i32 128}
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; OPT: !1 = !{i32 32, i32 4, i32 1}
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; OPT: !2 = !{i32 0, i32 32}
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; OPT: !3 = !{i32 0, i32 4}
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; OPT: !4 = !{i32 0, i32 1}
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; OPT: !5 = !{i32 1, i32 1, i32 1}
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; OPT: !6 = !{i32 0, i32 512}
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; OPT: !7 = !{i32 0, i32 1024}
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