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33b1222ec6
And a small utilities -- extract-section.py -- that helps extracting specific object file section and printing in textual format. This utility is just a workaround for tests inside `Encoding`. Hopefully in the future we can replace dependencies in those tests with existing tools (e.g. llvm-readobj). Please refer to this bug for more context: https://bugs.llvm.org/show_bug.cgi?id=49245 Note that since we don't have AsmParser for now, we are testing the MC part using MIR as input and put those tests under the `Encoding` folder. In the future when AsmParser (and disassembler) is finished, those tests will be moved to `test/MC/M68k`. Authors: myhsu, m4yers, glaubitz Differential Revision: https://reviews.llvm.org/D88392
96 lines
2.6 KiB
LLVM
96 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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define i64 @test1(i64 %A, i32 %B) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (12,%sp), %d0
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; CHECK-NEXT: add.l (4,%sp), %d0
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; CHECK-NEXT: move.l (8,%sp), %d1
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; CHECK-NEXT: rts
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%tmp12 = zext i32 %B to i64
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%tmp3 = shl i64 %tmp12, 32
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%tmp5 = add i64 %tmp3, %A
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ret i64 %tmp5
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}
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define void @test2(i32* inreg %a) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l %d0, %a0
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; CHECK-NEXT: add.l #128, (%a0)
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; CHECK-NEXT: rts
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%aa = load i32, i32* %a
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%b = add i32 %aa, 128
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store i32 %b, i32* %a
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ret void
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}
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define fastcc void @test2_fast(i32* inreg %a) nounwind {
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; CHECK-LABEL: test2_fast:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: add.l #128, (%a0)
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; CHECK-NEXT: rts
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%aa = load i32, i32* %a
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%b = add i32 %aa, 128
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store i32 %b, i32* %a
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ret void
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}
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define fastcc void @test3(i64* inreg %a) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: move.l #0, %d1
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; CHECK-NEXT: move.l #-2147483648, %d2
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; CHECK-NEXT: add.l (4,%a0), %d2
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; CHECK-NEXT: addx.l %d0, %d1
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; CHECK-NEXT: move.l %d2, (4,%a0)
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; CHECK-NEXT: move.l %d1, (%a0)
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: add.l #4, %sp
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; CHECK-NEXT: rts
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%aa = load i64, i64* %a
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%b = add i64 %aa, 2147483648
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store i64 %b, i64* %a
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ret void
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}
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define fastcc void @test4(i64* inreg %a) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: move.l #0, %d1
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; CHECK-NEXT: move.l #128, %d2
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; CHECK-NEXT: add.l (4,%a0), %d2
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; CHECK-NEXT: addx.l %d0, %d1
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; CHECK-NEXT: move.l %d2, (4,%a0)
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; CHECK-NEXT: move.l %d1, (%a0)
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: add.l #4, %sp
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; CHECK-NEXT: rts
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%aa = load i64, i64* %a
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%b = add i64 %aa, 128
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store i64 %b, i64* %a
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ret void
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}
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define fastcc i32 @test9(i32 %x, i32 %y) nounwind readnone {
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; CHECK-LABEL: test9:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub.l #10, %d0
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; CHECK-NEXT: seq %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: sub.l %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: rts
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%cmp = icmp eq i32 %x, 10
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%sub = sext i1 %cmp to i32
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%cond = add i32 %sub, %y
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ret i32 %cond
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}
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