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1e049bdc77
renamed since they were last spiffed up, or they just never had proper comments in the first place. llvm-svn: 13148
42 lines
1.9 KiB
TableGen
42 lines
1.9 KiB
TableGen
//===- SparcV9_Reg.td - SparcV9 Register definitions ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the SparcV9 register file
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//===----------------------------------------------------------------------===//
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// Ri - One of the 32 64 bit integer registers
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class Ri<bits<5> num> : Register {
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field bits<5> Num = num; // Numbers are identified with a 5 bit ID
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}
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let Namespace = "SparcV9" in {
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def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
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def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
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def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
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def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
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def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
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def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
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def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
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def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
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// Floating-point registers?
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// ...
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}
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// For fun, specify a register class.
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, O6, O7,
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L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5, I6, I7]>;
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