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e325c693a5
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
64 lines
3.1 KiB
C++
64 lines
3.1 KiB
C++
//===- MipsSchedule.td - Mips Scheduling Definitions ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across Mips chips sets. Based on GCC/Mips backend files.
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//===----------------------------------------------------------------------===//
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def ALU : FuncUnit;
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def IMULDIV : FuncUnit;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for Mips
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//===----------------------------------------------------------------------===//
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def IIAlu : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIXfer : InstrItinClass;
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def IIBranch : InstrItinClass;
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def IIHiLo : InstrItinClass;
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def IIImul : InstrItinClass;
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def IIIdiv : InstrItinClass;
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def IIFcvt : InstrItinClass;
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def IIFmove : InstrItinClass;
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def IIFcmp : InstrItinClass;
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def IIFadd : InstrItinClass;
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def IIFmulSingle : InstrItinClass;
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def IIFmulDouble : InstrItinClass;
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def IIFdivSingle : InstrItinClass;
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def IIFdivDouble : InstrItinClass;
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def IIFsqrtSingle : InstrItinClass;
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def IIFsqrtDouble : InstrItinClass;
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def IIFrecipFsqrtStep : InstrItinClass;
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def IIPseudo : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Mips Generic instruction itineraries.
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//===----------------------------------------------------------------------===//
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def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [
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InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
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InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,
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InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIHiLo , [InstrStage<1, [IMULDIV]>]>,
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InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
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InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
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InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIFadd , [InstrStage<4, [ALU]>]>,
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InstrItinData<IIFmulSingle , [InstrStage<7, [ALU]>]>,
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InstrItinData<IIFmulDouble , [InstrStage<8, [ALU]>]>,
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InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>,
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InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
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InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
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InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
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InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>
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]>;
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