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8767e9f9fd
The pseudo was using SSrc_b64, so it allowed folding immediates into the destination operand for a tail call to null. However, this is not a valid operand for the s_setpc_b64 this will be lowered to. Avoids printing the operand as an invalid immediate. Avoids a regression when tail calls are enabled in GlobalISel (somehow tail calls to null get deleted in the DAG).
45 lines
1.2 KiB
ArmAsm
45 lines
1.2 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
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s_mov_b32 v1, s2
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// GCN: error: invalid operand for instruction
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s_mov_b32 s1, v0
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// GCN: error: invalid operand for instruction
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s_mov_b32 s[1:2], s0
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// GCN: error: invalid register alignment
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s_mov_b32 s0, s[1:2]
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// GCN: error: invalid register alignment
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s_mov_b32 s220, s0
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// GCN: error: register index is out of range
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s_mov_b32 s0, s220
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// GCN: error: register index is out of range
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s_mov_b64 s1, s[0:1]
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// GCN: error: invalid operand for instruction
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s_mov_b64 s[0:1], s1
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// GCN: error: invalid operand for instruction
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// FIXME: This shoudl probably say failed to parse.
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s_mov_b32 s
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// GCN: error: invalid operand for instruction
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// Out of range register
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s_mov_b32 s102, 1
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// VI: error: register not available on this GPU
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s_mov_b32 s103, 1
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// VI: error: register not available on this GPU
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s_mov_b64 s[102:103], -1
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// VI: error: register not available on this GPU
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s_setpc_b64 0
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// GCN: error: invalid operand for instruction
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