Quentin Colombet cf0d20f78c [MachineBlockPlacement] Let the target optimize the branches at the end. ... After the layout of the basic blocks is set, the target may be able to get rid of unconditional branches to fallthrough blocks that the generic code does not catch. This happens any time TargetInstrInfo::AnalyzeBranch is not able to analyze all the branches involved in the terminators sequence, while still understanding a few of them. In such situation, AnalyzeBranch can directly modify the branches if it has been instructed to do so. This patch takes advantage of that. llvm-svn: 268328		2016-05-02 22:58:59 +00:00
..
AArch64	[AArch64] Set correct successors in CMPXCHG pseudo expansion.	2016-04-27 20:33:02 +00:00
AMDGPU	AMDGPU: Custom lower v2i32 loads and stores	2016-05-02 20:13:51 +00:00
ARM	[ARM] Set correct successors in CMPXCHG pseudo expansion.	2016-04-27 20:32:54 +00:00
BPF
CPP
Generic	Introduce llvm.load.relative intrinsic.	2016-04-22 21:18:02 +00:00
Hexagon	[Hexagon] Optimize addressing modes for load/store	2016-04-29 15:49:13 +00:00
Inputs
Lanai	[lanai] Add subword scheduling itineraries.	2016-04-20 18:28:55 +00:00
Mips	[mips][FastISel] A store is not a load.	2016-04-29 16:07:47 +00:00
MIR	ARM: fix handling of SUB immediates in peephole opt.	2016-05-02 18:30:08 +00:00
MSP430
NVPTX	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
PowerPC	[MBP] Use Function::optForSize() instead of checking OptimizeForSize directly.	2016-04-29 22:01:10 +00:00
SPARC	[SPARC] [SSP] Add support for LOAD_STACK_GUARD.	2016-04-26 10:37:14 +00:00
SystemZ	[SystemZ] Temporarily disable codegen test int-add-12.ll.	2016-05-02 10:42:47 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Rename memory_size intrinsic to current_memory	2016-05-02 17:25:22 +00:00
WinEH
X86	[MachineBlockPlacement] Let the target optimize the branches at the end.	2016-05-02 22:58:59 +00:00
XCore