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214 lines
8.5 KiB
TableGen
214 lines
8.5 KiB
TableGen
//===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips EVA ASE instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Instruction encodings
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//
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//===----------------------------------------------------------------------===//
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// Memory Load/Store EVA encodings
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class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBE>;
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class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBuE>;
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class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHE>;
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class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHuE>;
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class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWE>;
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class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SBE>;
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class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SHE>;
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class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWE>;
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// load/store left/right EVA encodings
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class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWLE>;
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class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWRE>;
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class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWLE>;
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class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWRE>;
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// Load-linked EVA, Store-conditional EVA encodings
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class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LLE>;
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class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SCE>;
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class TLBINV_ENC : TLB_FM<OPCODE6_TLBINV>;
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class TLBINVF_ENC : TLB_FM<OPCODE6_TLBINVF>;
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class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_CACHEE>;
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class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction descriptions
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//
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//===----------------------------------------------------------------------===//
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// Memory Load/Store EVA descriptions
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class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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bit canFoldAsLoad = 1;
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string BaseOpcode = instr_asm;
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bit mayLoad = 1;
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InstrItinClass Itinerary = itin;
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}
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class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>;
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class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>;
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class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>;
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class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>;
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class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
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class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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SDPatternOperator OpNode = null_frag,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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bit mayStore = 1;
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InstrItinClass Itinerary = itin;
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}
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class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, null_frag, II_SBE>;
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class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, null_frag, II_SHE>;
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class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, null_frag, II_SWE>;
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// Load/Store Left/Right EVA descriptions
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class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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string Constraints = "$src = $rt";
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bit canFoldAsLoad = 1;
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InstrItinClass Itinerary = itin;
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bit mayLoad = 1;
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bit mayStore = 0;
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}
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class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>;
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class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>;
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class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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InstrItinClass Itinerary = itin;
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bit mayLoad = 0;
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bit mayStore = 1;
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}
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class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>;
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class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>;
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// Load-linked EVA, Store-conditional EVA descriptions
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class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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bit mayLoad = 1;
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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}
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class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
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class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs GPROpnd:$dst);
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dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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bit mayStore = 1;
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string Constraints = "$rt = $dst";
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string DecoderMethod = "DecodeMemEVA";
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InstrItinClass Itinerary = itin;
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}
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class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
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class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins);
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string AsmString = instr_asm;
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list<dag> Pattern = [];
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InstrItinClass Itinerary = itin;
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}
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class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>;
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class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>;
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class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
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string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
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list<dag> Pattern = [];
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string BaseOpcode = instr_asm;
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string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
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InstrItinClass Itinerary = itin;
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}
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class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>;
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class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction definitions
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//
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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/// Load and Store EVA Instructions
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def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA;
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/// load/store left/right EVA
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def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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/// Load-linked EVA, Store-conditional EVA
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def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA;
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/// TLB invalidate instructions
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def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA;
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def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA;
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/// EVA versions of cache and pref
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def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA;
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def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA;
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}
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