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4d0c9d0af7
The damage done by physreg coalescing only depends on the number of instructions the extended physreg live range covers. This fixes PR9438. The heuristic is still luck-based, and physreg coalescing really should be disabled completely. We need a register allocator with better hinting support before that is possible. Convert a test to FileCheck and force spilling by inserting an extra call. The previous spilling behavior was dependent on misguided physreg coalescing decisions. llvm-svn: 127351
23 lines
889 B
LLVM
23 lines
889 B
LLVM
; RUN: llc -mcpu=yonah < %s
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; PR9438
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
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target triple = "i386-unknown-freebsd9.0"
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; The 'call fastcc' ties down %ebx, %ecx, and %edx.
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; A MUL8r ties down %al, leaving no GR32_ABCD registers available.
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; The coalescer can easily overallocate physical registers,
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; and register allocation fails.
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declare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind
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define i32 @cvtchar(i8* nocapture %sp) nounwind {
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%temp.i = alloca [2 x i8], align 1
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%tmp1 = load i8* %sp, align 1
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%div = udiv i8 %tmp1, 10
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%rem = urem i8 %div, 10
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%arrayidx.i = getelementptr inbounds [2 x i8]* %temp.i, i32 0, i32 0
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store i8 %rem, i8* %arrayidx.i, align 1
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%call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind
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ret i32 undef
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}
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