mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 13:02:52 +02:00
94d4d3db3b
Implementation of TargetInstrInfo::findCommutedOpIndices for MIPS target, restricting commutativity to second and third operand only for dpaadd_[su].df instructions therein. Prior to this change, there were cases where the vector that is to be added to the dot product of the other two could take a position other than the first one in the instruction, generating false output in the destination vector. Such behavior has been noticed in the two functions generating v2i64 output values so far. Other ones may exhibit such behavior as well, just not for the vector operands which are present in the test at the moment. Tests altered so that the function's first operand is a constant splat so that it can be loaded with a ldi instruction, since that is the case in which the erroneous instruction operand placement has occurred. We check that the register which is present in the ldi instruction is placed as the first operand in the corresponding dpadd instruction. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D30827 llvm-svn: 299223
165 lines
6.7 KiB
C++
165 lines
6.7 KiB
C++
//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips implementation of the TargetInstrInfo class.
|
|
//
|
|
// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
|
|
// order for MipsLongBranch pass to work correctly when the code has inline
|
|
// assembly. The returned value doesn't have to be the asm instruction's exact
|
|
// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
|
|
#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
|
|
|
|
#include "Mips.h"
|
|
#include "MipsRegisterInfo.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#define GET_INSTRINFO_HEADER
|
|
#include "MipsGenInstrInfo.inc"
|
|
|
|
namespace llvm {
|
|
class MipsSubtarget;
|
|
class MipsInstrInfo : public MipsGenInstrInfo {
|
|
virtual void anchor();
|
|
protected:
|
|
const MipsSubtarget &Subtarget;
|
|
unsigned UncondBrOpc;
|
|
|
|
public:
|
|
enum BranchType {
|
|
BT_None, // Couldn't analyze branch.
|
|
BT_NoBranch, // No branches found.
|
|
BT_Uncond, // One unconditional branch.
|
|
BT_Cond, // One conditional branch.
|
|
BT_CondUncond, // A conditional branch followed by an unconditional branch.
|
|
BT_Indirect // One indirct branch.
|
|
};
|
|
|
|
explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
|
|
|
|
static const MipsInstrInfo *create(MipsSubtarget &STI);
|
|
|
|
/// Branch Analysis
|
|
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const override;
|
|
|
|
unsigned removeBranch(MachineBasicBlock &MBB,
|
|
int *BytesRemoved = nullptr) const override;
|
|
|
|
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
const DebugLoc &DL,
|
|
int *BytesAdded = nullptr) const override;
|
|
|
|
bool
|
|
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
|
|
|
BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify,
|
|
SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
|
|
|
|
/// Determine the opcode of a non-delay slot form for a branch if one exists.
|
|
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
|
|
|
|
/// Predicate to determine if an instruction can go in a forbidden slot.
|
|
bool SafeInForbiddenSlot(const MachineInstr &MI) const;
|
|
|
|
/// Predicate to determine if an instruction has a forbidden slot.
|
|
bool HasForbiddenSlot(const MachineInstr &MI) const;
|
|
|
|
/// Insert nop instruction when hazard condition is found
|
|
void insertNoop(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const override;
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
|
|
|
|
virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
|
|
|
|
/// Return the number of bytes of code the specified instruction may be.
|
|
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
|
|
|
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const override {
|
|
storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
|
|
}
|
|
|
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const override {
|
|
loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
|
|
}
|
|
|
|
virtual void storeRegToStack(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
int64_t Offset) const = 0;
|
|
|
|
virtual void loadRegFromStack(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI,
|
|
int64_t Offset) const = 0;
|
|
|
|
virtual void adjustStackPtr(unsigned SP, int64_t Amount,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const = 0;
|
|
|
|
/// Create an instruction which has the same operands and memory operands
|
|
/// as MI but has a new opcode.
|
|
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
|
|
unsigned &SrcOpIdx2) const override;
|
|
|
|
protected:
|
|
bool isZeroImm(const MachineOperand &op) const;
|
|
|
|
MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
|
|
MachineMemOperand::Flags Flags) const;
|
|
|
|
private:
|
|
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
|
|
|
|
void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
|
MachineBasicBlock *&BB,
|
|
SmallVectorImpl<MachineOperand> &Cond) const;
|
|
|
|
void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
|
|
};
|
|
|
|
/// Create MipsInstrInfo objects.
|
|
const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
|
|
const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
|
|
|
|
}
|
|
|
|
#endif
|