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055a23f745
Leverage ARM ELF build attribute section to create ELF attribute section for RISC-V. Extract the common part of parsing logic for this section into ELFAttributeParser.[cpp|h] and ELFAttributes.[cpp|h]. Differential Revision: https://reviews.llvm.org/D74023
38 lines
1.0 KiB
ArmAsm
38 lines
1.0 KiB
ArmAsm
## Arch string without version.
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# RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
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# RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
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.attribute arch, "rv32i"
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# CHECK: attribute 5, "rv32i2p0"
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.attribute arch, "rv32i2"
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# CHECK: attribute 5, "rv32i2p0"
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.attribute arch, "rv32i2p"
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# CHECK: attribute 5, "rv32i2p0"
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.attribute arch, "rv32i2p0"
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# CHECK: attribute 5, "rv32i2p0"
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.attribute arch, "rv32i2_m2"
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# CHECK: attribute 5, "rv32i2p0_m2p0"
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.attribute arch, "rv32i2_ma"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0"
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.attribute arch, "rv32g"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
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.attribute arch, "rv32imafdc"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
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.attribute arch, "rv32i2p0_mafdc"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
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.attribute arch, "rv32ima2p0_fdc"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
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.attribute arch, "rv32ima2p_fdc"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
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