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055a23f745
Leverage ARM ELF build attribute section to create ELF attribute section for RISC-V. Extract the common part of parsing logic for this section into ELFAttributeParser.[cpp|h] and ELFAttributes.[cpp|h]. Differential Revision: https://reviews.llvm.org/D74023
35 lines
885 B
ArmAsm
35 lines
885 B
ArmAsm
## Test .attribute effects.
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## We do not provide '-mattr=' and '.option rvc' and enable extensions through
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## '.attribute arch'.
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# RUN: llvm-mc -triple riscv32 -filetype=obj %s \
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# RUN: | llvm-objdump --triple=riscv32 -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -triple riscv64 -filetype=obj %s \
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# RUN: | llvm-objdump --triple=riscv64 -d -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
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# CHECK-INST: lr.w t0, (t1)
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lr.w t0, (t1)
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# CHECK-INST: c.addi a3, -32
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c.addi a3, -32
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# CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
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fmadd.d f10, f11, f12, f13, dyn
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# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
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fmadd.s f10, f11, f12, f13, dyn
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# CHECK-INST: addi ra, sp, 2
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addi ra, sp, 2
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# CHECK-INST: mul a4, ra, s0
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mul a4, ra, s0
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# CHECK-INST: addw a2, a3, a4
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addw a2, a3, a4
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