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39932105f0
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
9 lines
388 B
ArmAsm
9 lines
388 B
ArmAsm
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbc < %s 2>&1 | FileCheck %s
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# Too few operands
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clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Too few operands
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clmulr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Too few operands
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clmulh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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