mirror of
https://github.com/RPCS3/llvm-mirror.git
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c6b3072fd0
Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
237 lines
5.6 KiB
ArmAsm
237 lines
5.6 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
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# These user mode CSR register names are RV32 only, but RV64
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# can encode and disassemble these registers if given their value.
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##################################
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# User Counter and Timers
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##################################
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# cycleh
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# uimm12
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# CHECK-INST: csrrs t2, 3200, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3200
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csrrs t2, 0xC80, zero
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# timeh
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# uimm12
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# CHECK-INST: csrrs t2, 3201, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3201
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csrrs t2, 0xC81, zero
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# instreth
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# uimm12
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# CHECK-INST: csrrs t2, 3202, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3202
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csrrs t2, 0xC82, zero
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# hpmcounter3h
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# uimm12
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# CHECK-INST: csrrs t2, 3203, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3203
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csrrs t2, 0xC83, zero
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# hpmcounter4h
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# uimm12
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# CHECK-INST: csrrs t2, 3204, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3204
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csrrs t2, 0xC84, zero
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# hpmcounter5h
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# uimm12
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# CHECK-INST: csrrs t2, 3205, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3205
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csrrs t2, 0xC85, zero
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# hpmcounter6h
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# uimm12
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# CHECK-INST: csrrs t2, 3206, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x60,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3206
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csrrs t2, 0xC86, zero
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# hpmcounter7h
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# uimm12
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# CHECK-INST: csrrs t2, 3207, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x70,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3207
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csrrs t2, 0xC87, zero
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# hpmcounter8h
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# uimm12
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# CHECK-INST: csrrs t2, 3208, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x80,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3208
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csrrs t2, 0xC88, zero
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# hpmcounter9h
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# uimm12
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# CHECK-INST: csrrs t2, 3209, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x90,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3209
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csrrs t2, 0xC89, zero
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# hpmcounter10h
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# uimm12
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# CHECK-INST: csrrs t2, 3210, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3210
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csrrs t2, 0xC8A, zero
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# hpmcounter11h
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# uimm12
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# CHECK-INST: csrrs t2, 3211, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3211
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csrrs t2, 0xC8B, zero
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# hpmcounter12h
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# uimm12
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# CHECK-INST: csrrs t2, 3212, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3212
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csrrs t2, 0xC8C, zero
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# hpmcounter13h
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# uimm12
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# CHECK-INST: csrrs t2, 3213, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3213
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csrrs t2, 0xC8D, zero
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# hpmcounter14h
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# uimm12
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# CHECK-INST: csrrs t2, 3214, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3214
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csrrs t2, 0xC8E, zero
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# hpmcounter15h
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# uimm12
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# CHECK-INST: csrrs t2, 3215, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xc8]
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# CHECK-INST-ALIAS: csrr t2, 3215
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csrrs t2, 0xC8F, zero
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# hpmcounter16h
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# uimm12
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# CHECK-INST: csrrs t2, 3216, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3216
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csrrs t2, 0xC90, zero
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# hpmcounter17h
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# uimm12
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# CHECK-INST: csrrs t2, 3217, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3217
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csrrs t2, 0xC91, zero
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# hpmcounter18h
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# uimm12
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# CHECK-INST: csrrs t2, 3218, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3218
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csrrs t2, 0xC92, zero
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# hpmcounter19h
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# uimm12
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# CHECK-INST: csrrs t2, 3219, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3219
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csrrs t2, 0xC93, zero
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# hpmcounter20h
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# uimm12
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# CHECK-INST: csrrs t2, 3220, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3220
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csrrs t2, 0xC94, zero
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# hpmcounter21h
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# uimm12
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# CHECK-INST: csrrs t2, 3221, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3221
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csrrs t2, 0xC95, zero
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# hpmcounter22h
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# uimm12
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# CHECK-INST: csrrs t2, 3222, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x60,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3222
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csrrs t2, 0xC96, zero
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# hpmcounter23h
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# uimm12
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# CHECK-INST: csrrs t2, 3223, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x70,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3223
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csrrs t2, 0xC97, zero
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# hpmcounter24h
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# uimm12
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# CHECK-INST: csrrs t2, 3224, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x80,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3224
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csrrs t2, 0xC98, zero
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# hpmcounter25h
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# uimm12
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# CHECK-INST: csrrs t2, 3225, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x90,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3225
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csrrs t2, 0xC99, zero
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# hpmcounter26h
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# uimm12
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# CHECK-INST: csrrs t2, 3226, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3226
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csrrs t2, 0xC9A, zero
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# hpmcounter27h
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# uimm12
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# CHECK-INST: csrrs t2, 3227, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3227
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csrrs t2, 0xC9B, zero
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# hpmcounter28h
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# uimm12
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# CHECK-INST: csrrs t2, 3228, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3228
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csrrs t2, 0xC9C, zero
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# hpmcounter29h
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# uimm12
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# CHECK-INST: csrrs t2, 3229, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3229
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csrrs t2, 0xC9D, zero
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# hpmcounter30h
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# uimm12
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# CHECK-INST: csrrs t2, 3230, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3230
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csrrs t2, 0xC9E, zero
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# hpmcounter31h
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# uimm12
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# CHECK-INST: csrrs t2, 3231, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xc9]
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# CHECK-INST-ALIAS: csrr t2, 3231
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csrrs t2, 0xC9F, zero
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