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39932105f0
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
54 lines
2.0 KiB
ArmAsm
54 lines
2.0 KiB
ArmAsm
# With B extension:
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
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# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
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# With Bitmanip base extension:
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
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# RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0
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# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00]
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addiwu t0, t1, 0
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# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
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# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
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slliu.w t0, t1, 0
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# CHECK-ASM-AND-OBJ: addwu t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a]
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addwu t0, t1, t2
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# CHECK-ASM-AND-OBJ: subwu t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a]
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subwu t0, t1, t2
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# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
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addu.w t0, t1, t2
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# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48]
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subu.w t0, t1, t2
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# CHECK-ASM-AND-OBJ: slow t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
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slow t0, t1, t2
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# CHECK-ASM-AND-OBJ: srow t0, t1, t2
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# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
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srow t0, t1, t2
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# CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
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# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]
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sloiw t0, t1, 0
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# CHECK-ASM-AND-OBJ: sroiw t0, t1, 0
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# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x20]
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sroiw t0, t1, 0
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# CHECK-ASM-AND-OBJ: clzw t0, t1
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# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
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clzw t0, t1
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# CHECK-ASM-AND-OBJ: ctzw t0, t1
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# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
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ctzw t0, t1
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# CHECK-ASM-AND-OBJ: pcntw t0, t1
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# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
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pcntw t0, t1
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