1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/MC/RISCV/rv64zbbp-invalid.s
Paolo Savini 39932105f0 [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
This adds the instruction encoding and mnenomics for the proposed
RISC-V Bit Manipulation extension (version 0.92). It is implemented with
each category of instruction as its own target feature, with the 'b'
extension feature enabling all options. Since this extension is not yet
ratified, all target features are prefixed with 'experimental-' to note
their status.

Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:04:22 +01:00

16 lines
821 B
ArmAsm

# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb,experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands
rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
rorw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
roriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
roriw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
roriw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
# Too few operands
packw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
packuw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction