Zhan Jun Liau 26394d50f8 [SystemZ] Add missing classes and instructions ... Summary: Add instruction formats E, RSI, SSd, SSE, and SSF. Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out those formats. Reviewers: uweigand Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23179 llvm-svn: 277822		2016-08-05 15:14:34 +00:00
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AArch64	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AMDGPU	[AMDGPU] refactor DS instruction definitions. NFC.	2016-08-01 14:21:30 +00:00
ARM	Fix handling of end-of-line preprocessor comments Attempt 2	2016-08-02 19:17:54 +00:00
AsmParser	Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"	2016-08-01 23:00:01 +00:00
COFF	[codeview] Shrink inlined call site line info tables	2016-07-14 23:47:15 +00:00
Disassembler	[SystemZ] Add missing classes and instructions	2016-08-05 15:14:34 +00:00
ELF	Add initial support for R_386_GOT32X.	2016-07-06 21:19:11 +00:00
Hexagon	Remove redundant -mattr options from llvm-objdump commands.	2016-06-16 15:47:19 +00:00
Lanai	[lanai] Add more tests for assembly of conditional ALU ops	2016-07-11 17:58:16 +00:00
MachO
Markup
Mips	[mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions	2016-08-04 11:22:52 +00:00
PowerPC	Add aliases for mfvrsave/mtvrsave.	2016-06-09 23:27:48 +00:00
Sparc	Don't pass a Reloc::Model to MC.	2016-05-18 11:58:50 +00:00
SystemZ	[SystemZ] Add missing classes and instructions	2016-08-05 15:14:34 +00:00
X86	[AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vcvttss2usi{l|q}, vcvttsd2usi{l|q} instructions.	2016-08-03 10:58:05 +00:00