1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
llvm-mirror/test/CodeGen/Hexagon/misaligned-access.ll
Jyotsna Verma f2d3c71cf4 Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.

llvm-svn: 177103
2013-03-14 19:08:03 +00:00

17 lines
450 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s
; Check that the mis-aligned load doesn't cause compiler to assert.
declare i32 @_hi(i64) #1
@temp1 = common global i32 0, align 4
define i32 @CSDRSEARCH_executeSearchManager() #0 {
entry:
%temp = alloca i32, align 4
%0 = load i32* @temp1, align 4
store i32 %0, i32* %temp, align 4
%1 = bitcast i32* %temp to i64*
%2 = load i64* %1, align 8
%call = call i32 @_hi(i64 %2)
ret i32 %call
}