1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
llvm-mirror/test/CodeGen/Mips/buildpairextractelementf64.ll
Daniel Sanders fc1f878e70 [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves
Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.

Differential Revision: http://reviews.llvm.org/D4483

llvm-svn: 212936
2014-07-14 12:41:31 +00:00

41 lines
1.1 KiB
LLVM

; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
@a = external global i32
; ALL-LABEL: f:
; NO-MFHC1: mtc1
; NO-MFHC1: mtc1
; HAS-MFHC1-DAG: mtc1
; HAS-MFHC1-DAG: mthc1
define double @f(i32 %a1, double %d) nounwind {
entry:
store i32 %a1, i32* @a, align 4
%add = fadd double %d, 2.000000e+00
ret double %add
}
; ALL-LABEL: f3:
; NO-MFHC1: mfc1
; NO-MFHC1: mfc1
; HAS-MFHC1-DAG: mfc1
; HAS-MFHC1-DAG: mfhc1
define void @f3(double %d, i32 %a1) nounwind {
entry:
tail call void @f2(i32 %a1, double %d) nounwind
ret void
}
declare void @f2(i32, double)