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80 lines
2.9 KiB
TableGen
80 lines
2.9 KiB
TableGen
//===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARC register file
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//===----------------------------------------------------------------------===//
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class ARCReg<string n, list<string> altNames> : Register<n, altNames> {
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field bits<6> HwEncoding;
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let Namespace = "ARC";
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}
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// Registers are identified with 6-bit ID numbers.
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// Core - 32-bit core registers
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class Core<int num, string n, list<string>altNames=[]> : ARCReg<n, altNames> {
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let HWEncoding = num;
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}
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class Status<string n> : ARCReg<n, []> {
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}
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// Integer registers
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def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
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def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
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def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
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def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
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let CostPerUse=1 in {
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def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
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def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
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def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
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def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
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def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
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def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
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def R10 : Core<10, "%r10">, DwarfRegNum<[10]>;
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def R11 : Core<11, "%r11">, DwarfRegNum<[11]>;
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}
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def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
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def R13 : Core<13, "%r13">, DwarfRegNum<[13]>;
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def R14 : Core<14, "%r14">, DwarfRegNum<[14]>;
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def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
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let CostPerUse=1 in {
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def R16 : Core<16, "%r16">, DwarfRegNum<[16]>;
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def R17 : Core<17, "%r17">, DwarfRegNum<[17]>;
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def R18 : Core<18, "%r18">, DwarfRegNum<[18]>;
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def R19 : Core<19, "%r19">, DwarfRegNum<[19]>;
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def R20 : Core<20, "%r20">, DwarfRegNum<[20]>;
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def R21 : Core<21, "%r21">, DwarfRegNum<[21]>;
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def R22 : Core<22, "%r22">, DwarfRegNum<[22]>;
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def R23 : Core<23, "%r23">, DwarfRegNum<[23]>;
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def R24 : Core<24, "%r24">, DwarfRegNum<[24]>;
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def R25 : Core<25, "%r25">, DwarfRegNum<[25]>;
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def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
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def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;
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def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>;
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def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;
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def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
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def BLINK: Core<31, "%blink">, DwarfRegNum<[31]>;
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def STATUS32 : Status<"status32">, DwarfRegNum<[32]>;
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}
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// Register classes.
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//
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def GPR32: RegisterClass<"ARC", [i32], 32,
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(add R0, R1, R2, R3,
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R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
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def GPR_S : RegisterClass<"ARC", [i32], 8,
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(add R0, R1, R2, R3, R12, R13, R14, R15)>;
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