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430 lines
20 KiB
TableGen
430 lines
20 KiB
TableGen
//===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 instructions that are generally used in
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// privileged modes. These are not typically used by the compiler, but are
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// supported for the assembler and disassembler.
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//
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//===----------------------------------------------------------------------===//
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let Defs = [RAX, RDX] in
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def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
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let Defs = [RAX, RCX, RDX] in
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def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
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// CPU flow control instructions
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let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
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def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
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}
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def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
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def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
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// Interrupt and SysCall Instructions.
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let Uses = [EFLAGS] in
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
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[(int_x86_int (i8 3))]>;
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// The long form of "int $3" turns into int3 as a size optimization.
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// FIXME: This doesn't work because InstAlias can't match immediate constants.
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//def : InstAlias<"int\t$3", (INT3)>;
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def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
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[(int_x86_int imm:$trap)]>;
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def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
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def SYSRETL : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
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def SYSRETQ :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
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Requires<[In64BitMode]>;
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def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
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def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
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Requires<[In32BitMode]>;
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def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
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Requires<[In64BitMode]>;
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def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
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def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Input/Output Instructions.
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//
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let Defs = [AL], Uses = [DX] in
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def IN8rr : I<0xEC, RawFrm, (outs), (ins),
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"in{b}\t{%dx, %al|%AL, %DX}", []>;
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let Defs = [AX], Uses = [DX] in
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def IN16rr : I<0xED, RawFrm, (outs), (ins),
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"in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
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let Defs = [EAX], Uses = [DX] in
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def IN32rr : I<0xED, RawFrm, (outs), (ins),
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"in{l}\t{%dx, %eax|%EAX, %DX}", []>;
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let Defs = [AL] in
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def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
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"in{b}\t{$port, %al|%AL, $port}", []>;
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let Defs = [AX] in
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def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
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let Defs = [EAX] in
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def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{l}\t{$port, %eax|%EAX, $port}", []>;
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let Uses = [DX, AL] in
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def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
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"out{b}\t{%al, %dx|%DX, %AL}", []>;
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let Uses = [DX, AX] in
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def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
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"out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
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let Uses = [DX, EAX] in
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def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
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"out{l}\t{%eax, %dx|%DX, %EAX}", []>;
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let Uses = [AL] in
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def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
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"out{b}\t{%al, $port|$port, %AL}", []>;
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let Uses = [AX] in
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def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
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let Uses = [EAX] in
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def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{l}\t{%eax, $port|$port, %EAX}", []>;
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def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
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def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
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def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
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//===----------------------------------------------------------------------===//
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// Moves to and from debug registers
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def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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//===----------------------------------------------------------------------===//
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// Moves to and from control registers
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def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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//===----------------------------------------------------------------------===//
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// Segment override instruction prefixes
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def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
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def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
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def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
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def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
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def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
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def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
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//===----------------------------------------------------------------------===//
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// Moves to and from segment registers.
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//
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def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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//===----------------------------------------------------------------------===//
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// Segmentation support instructions.
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
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def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
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def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
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def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
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def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
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"str{w}\t{$dst}", []>, TB, OpSize;
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def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
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"str{l}\t{$dst}", []>, TB;
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def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
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"str{q}\t{$dst}", []>, TB;
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def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
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"str{w}\t{$dst}", []>, TB;
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def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
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"ltr{w}\t{$src}", []>, TB;
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def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
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"ltr{w}\t{$src}", []>, TB;
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def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
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"push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
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"push{l}\t%cs", []>, Requires<[In32BitMode]>;
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def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
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"push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
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"push{l}\t%ss", []>, Requires<[In32BitMode]>;
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def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
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"push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
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"push{l}\t%ds", []>, Requires<[In32BitMode]>;
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def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
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"push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
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"push{l}\t%es", []>, Requires<[In32BitMode]>;
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def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
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"push{w}\t%fs", []>, OpSize, TB;
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def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
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"push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
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def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
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"push{w}\t%gs", []>, OpSize, TB;
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def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
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"push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
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def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
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"push{q}\t%fs", []>, TB;
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def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
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"push{q}\t%gs", []>, TB;
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// No "pop cs" instruction.
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def POPSS16 : I<0x17, RawFrm, (outs), (ins),
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"pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
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def POPSS32 : I<0x17, RawFrm, (outs), (ins),
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"pop{l}\t%ss", []> , Requires<[In32BitMode]>;
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def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
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"pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
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def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
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"pop{l}\t%ds", []> , Requires<[In32BitMode]>;
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def POPES16 : I<0x07, RawFrm, (outs), (ins),
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"pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
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def POPES32 : I<0x07, RawFrm, (outs), (ins),
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"pop{l}\t%es", []> , Requires<[In32BitMode]>;
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def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
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"pop{w}\t%fs", []>, OpSize, TB;
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def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
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"pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
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def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
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"pop{q}\t%fs", []>, TB;
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def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
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"pop{w}\t%gs", []>, OpSize, TB;
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def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
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"pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
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def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
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"pop{q}\t%gs", []>, TB;
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def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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"lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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"lds{l}\t{$src, $dst|$dst, $src}", []>;
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def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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"lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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"lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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"les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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"les{l}\t{$src, $dst|$dst, $src}", []>;
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def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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"lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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"lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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"lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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"lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
|
"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
|
|
def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
|
|
"verr\t$seg", []>, TB;
|
|
def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
|
|
"verr\t$seg", []>, TB;
|
|
def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
|
|
"verw\t$seg", []>, TB;
|
|
def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
|
"verw\t$seg", []>, TB;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Descriptor-table support instructions
|
|
|
|
def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
|
"sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
|
|
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
|
"sgdt\t$dst", []>, TB;
|
|
def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
|
"sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
|
|
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
|
"sidt\t$dst", []>, TB;
|
|
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
|
"sldt{w}\t$dst", []>, TB, OpSize;
|
|
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
|
"sldt{w}\t$dst", []>, TB;
|
|
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
|
"sldt{l}\t$dst", []>, TB;
|
|
|
|
// LLDT is not interpreted specially in 64-bit mode because there is no sign
|
|
// extension.
|
|
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
|
|
"sldt{q}\t$dst", []>, TB;
|
|
def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
|
"sldt{q}\t$dst", []>, TB;
|
|
|
|
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
|
"lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
|
|
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
|
"lgdt\t$src", []>, TB;
|
|
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
|
"lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
|
|
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
|
"lidt\t$src", []>, TB;
|
|
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
|
"lldt{w}\t$src", []>, TB;
|
|
def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
|
"lldt{w}\t$src", []>, TB;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Specialized register support
|
|
def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
|
def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
|
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
|
|
|
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
|
"smsw{w}\t$dst", []>, OpSize, TB;
|
|
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
|
"smsw{l}\t$dst", []>, TB;
|
|
// no m form encodable; use SMSW16m
|
|
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
|
"smsw{q}\t$dst", []>, TB;
|
|
|
|
// For memory operands, there is only a 16-bit form
|
|
def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
|
|
"smsw{w}\t$dst", []>, TB;
|
|
|
|
def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
|
"lmsw{w}\t$src", []>, TB;
|
|
def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
|
"lmsw{w}\t$src", []>, TB;
|
|
|
|
def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Cache instructions
|
|
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
|
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
|
|
|
|
let Defs = [RDX, RAX], Uses = [RCX] in
|
|
def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
|
|
|
|
let Uses = [RDX, RAX, RCX] in
|
|
def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VIA PadLock crypto instructions
|
|
let Defs = [RAX, RDI], Uses = [RDX, RDI] in
|
|
def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
|
|
|
|
def : InstAlias<"xstorerng", (XSTORE)>;
|
|
|
|
let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
|
|
def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
|
|
def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
|
|
def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
|
|
def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
|
|
def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
|
|
}
|
|
|
|
let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
|
|
def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
|
|
def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
|
|
}
|
|
let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
|
|
def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
|