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AsmParser
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[RISCV] Support ABI checking with per function target-features
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2020-01-15 02:30:43 -08:00 |
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Disassembler
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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MCTargetDesc
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[RISCV] Support ABI checking with per function target-features
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2020-01-15 02:30:43 -08:00 |
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CMakeLists.txt
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LLVMBuild.txt
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RISCV.h
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RISCV.td
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[RISCV] Improve assembler missing feature warnings
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2019-12-10 16:44:48 +00:00 |
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RISCVAsmPrinter.cpp
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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RISCVCallingConv.td
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[RISCV] Rename FPRs and use Register arithmetic
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2019-09-27 15:49:10 +00:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandPseudoInsts.cpp
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[RISCV] Use addi rather than add x0
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2019-11-14 18:43:38 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Allow shrink wrapping for RISC-V
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2020-01-14 18:59:11 +00:00 |
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RISCVFrameLowering.h
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[RISCV] Handle variable sized objects with the stack need to be realigned
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2019-11-16 12:39:53 +08:00 |
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RISCVInstrFormats.td
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RISCVInstrFormatsC.td
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RISCVInstrInfo.cpp
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[RISCV] Enable the machine outliner for RISC-V
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2019-12-19 16:41:53 +00:00 |
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RISCVInstrInfo.h
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[RISCV] Enable the machine outliner for RISC-V
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2019-12-19 16:41:53 +00:00 |
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RISCVInstrInfo.td
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Fix typo "psuedo" in comments
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2020-01-03 14:05:58 +00:00 |
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RISCVInstrInfoA.td
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[RISCV] Check register class for AMO memory operands
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2020-01-13 00:50:37 +00:00 |
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RISCVInstrInfoC.td
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[RISCV] Added missing ImmLeaf predicates
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2019-10-04 23:42:07 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32)
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2019-11-26 14:26:31 +00:00 |
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RISCVInstrInfoF.td
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[RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)
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2019-10-03 15:47:28 +00:00 |
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RISCVInstrInfoM.td
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RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
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[SelectionDAG] Disallow indirect "i" constraint
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2019-12-29 16:50:42 -08:00 |
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RISCVISelLowering.cpp
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[RISCV] Support ABI checking with per function target-features
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2020-01-15 02:30:43 -08:00 |
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RISCVISelLowering.h
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CodeGen: Use LLT instead of EVT in getRegisterByName
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2020-01-09 17:37:52 -05:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Handle variable sized objects with the stack need to be realigned
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2019-11-16 12:39:53 +08:00 |
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RISCVRegisterInfo.h
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[RISCV] Add support for -ffixed-xX flags
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2019-10-22 21:25:01 +01:00 |
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RISCVRegisterInfo.td
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[RISCV] Rename FPRs and use Register arithmetic
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2019-09-27 15:49:10 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Add support for -ffixed-xX flags
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2019-10-22 21:25:01 +01:00 |
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RISCVSubtarget.h
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[RISCV] Add support for -ffixed-xX flags
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2019-10-22 21:25:01 +01:00 |
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RISCVSystemOperands.td
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RISCVTargetMachine.cpp
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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RISCVTargetMachine.h
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[RISCV] Add subtargets initialized with target feature
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2019-12-17 09:34:01 -08:00 |
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RISCVTargetObjectFile.cpp
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Revert "Honor -fuse-init-array when os is not specified on x86"
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2019-12-17 07:36:59 -08:00 |
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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Rename TTI::getIntImmCost for instructions and intrinsics
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2019-12-11 18:00:20 -08:00 |
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RISCVTargetTransformInfo.h
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Rename TTI::getIntImmCost for instructions and intrinsics
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2019-12-11 18:00:20 -08:00 |
