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8a77617721
Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
60 lines
2.5 KiB
LLVM
60 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; Check that building up a vector w/ only one non-zero lane initializes
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; intelligently.
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define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
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; CHECK-LABEL: one_lane:
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; CHECK: dup.16b v[[REG:[0-9]+]], wzr
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; CHECK-NEXT: mov.b v[[REG]][0], w1
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; v and q are aliases, and str is preferred against st.16b when possible
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; rdar://11246289
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; CHECK: str q[[REG]], [x0]
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; CHECK: ret
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%conv = trunc i32 %skip0 to i8
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%vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0
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%tmp = bitcast i32* %out_int to <4 x i32>*
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%tmp1 = bitcast <16 x i8> %vset_lane to <4 x i32>
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store <4 x i32> %tmp1, <4 x i32>* %tmp, align 16
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ret void
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}
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; Check that building a vector from floats doesn't insert an unnecessary
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; copy for lane zero.
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define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
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; CHECK-LABEL: foo:
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; CHECK-NOT: mov.s v0[0], v0[0]
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; CHECK: mov.s v0[1], v1[0]
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; CHECK: mov.s v0[2], v2[0]
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; CHECK: mov.s v0[3], v3[0]
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; CHECK: ret
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%1 = insertelement <4 x float> undef, float %a, i32 0
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%2 = insertelement <4 x float> %1, float %b, i32 1
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%3 = insertelement <4 x float> %2, float %c, i32 2
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%4 = insertelement <4 x float> %3, float %d, i32 3
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ret <4 x float> %4
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}
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define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
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; CHECK-LABEL: build_all_zero:
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; CHECK: mov w[[GREG:[0-9]+]], #44672
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; CHECK-NEXT: fmov s[[FREG:[0-9]+]], w[[GREG]]
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; CHECK-NEXT: mul.8h v0, v0, v[[FREG]]
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%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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ret <8 x i16> %c
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}
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; There is an optimization in DAG Combiner as following:
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; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
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; -> (BUILD_VECTOR A, B, ..., C, D, ...)
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; This case checks when A,B and C,D are different types, there should be no
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; assertion failure.
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define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
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; CHECK-LABEL: concat_2_build_vector:
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; CHECK: movi
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%vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
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%vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
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%shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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