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2872193f2e
Summary:
This bug seems to have gone unnoticed because critical cases with LDS
instructions are eliminated by the peephole optimizer.
However, equivalent situations arise with buffer loads and stores
as well, so this fixes regressions since r317751 ("AMDGPU: Merge
S_BUFFER_LOAD_DWORD_IMM into x2, x4").
Fixes at least:
KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs
KHR-GL45.cull_distance.functional
piglit tes-input-gl_ClipDistance.shader_test
... and probably more
Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d
Reviewers: arsenm, mareko, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D40303
llvm-svn: 318829
71 lines
2.4 KiB
YAML
71 lines
2.4 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
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# Check that SILoadStoreOptimizer honors memory dependencies between moved
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# instructions.
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#
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# The following IR snippet would usually be optimized by the peephole optimizer.
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# However, an equivalent situation can occur with buffer instructions as well.
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# CHECK-LABEL: name: mem_dependency
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# CHECK: DS_READ2_B32 %0, 0, 1,
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# CHECK: DS_WRITE_B32 %0, killed %1, 64,
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# CHECK: DS_READ2_B32 %0, 16, 17,
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# CHECK: DS_WRITE_B32 killed %0, %5, 0
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--- |
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define amdgpu_kernel void @mem_dependency(i32 addrspace(3)* %ptr.0) nounwind {
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%ptr.4 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 1
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%ptr.64 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 16
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%1 = load i32, i32 addrspace(3)* %ptr.0
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store i32 %1, i32 addrspace(3)* %ptr.64
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%2 = load i32, i32 addrspace(3)* %ptr.64
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%3 = load i32, i32 addrspace(3)* %ptr.4
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%4 = add i32 %2, %3
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store i32 %4, i32 addrspace(3)* %ptr.0
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ret void
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}
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...
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---
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name: mem_dependency
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%vgpr0', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: %vgpr0
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%1:vgpr_32 = COPY %vgpr0
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%m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit %m0, implicit %exec :: (load 4 from %ir.ptr.0)
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DS_WRITE_B32 %1, killed %2, 64, 0, implicit %m0, implicit %exec :: (store 4 into %ir.ptr.64)
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; Make this load unmergeable, to tempt SILoadStoreOptimizer into merging the
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; other two loads.
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%6:vreg_64 = DS_READ2_B32 %1, 16, 17, 0, implicit %m0, implicit %exec :: (load 8 from %ir.ptr.64, align 4)
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%3:vgpr_32 = COPY %6.sub0
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%4:vgpr_32 = DS_READ_B32 %1, 4, 0, implicit %m0, implicit %exec :: (load 4 from %ir.ptr.4)
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%5:vgpr_32 = V_ADD_I32_e32 killed %3, killed %4, implicit-def %vcc, implicit %exec
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DS_WRITE_B32 killed %1, %5, 0, 0, implicit killed %m0, implicit %exec :: (store 4 into %ir.ptr.0)
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S_ENDPGM
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...
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