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7a480fde07
This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
150 lines
3.7 KiB
LLVM
150 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
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define i32 @test1a(i32 %a, i32 %b) {
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; CHECK-LABEL: test1a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB0_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test1b(i32 %a, i32 %b) {
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; CHECK-LABEL: test1b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB1_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB1_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test2a(i32 %a, i32 %b) {
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; CHECK-LABEL: test2a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB2_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB2_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test2b(i32 %a, i32 %b) {
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; CHECK-LABEL: test2b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB3_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB3_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test3a(i32 %a, i32 %b) {
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; CHECK-LABEL: test3a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB4_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB4_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = select i1 %cmp, i32 0, i32 4
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ret i32 %cond
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}
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define i32 @test3b(i32 %a, i32 %b) {
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; CHECK-LABEL: test3b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: beq .LBB5_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r2, r3
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; CHECK-NEXT: .LBB5_2: @ %entry
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; CHECK-NEXT: lsls r0, r2, #2
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = select i1 %cmp, i32 4, i32 0
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ret i32 %cond
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}
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; FIXME: This one hasn't changed actually
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; but could look like test3b
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define i32 @test4a(i32 %a, i32 %b) {
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; CHECK-LABEL: test4a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB6_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB6_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = select i1 %cmp, i32 0, i32 4
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ret i32 %cond
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}
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define i32 @test4b(i32 %a, i32 %b) {
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; CHECK-LABEL: test4b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: bne .LBB7_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r2, r3
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; CHECK-NEXT: .LBB7_2: @ %entry
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; CHECK-NEXT: lsls r0, r2, #2
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = select i1 %cmp, i32 4, i32 0
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ret i32 %cond
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}
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