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llvm-mirror/lib/Target/RISCV
Hsiangkai Wang cffdb541a0 [RISCV] Define vector compare intrinsics.
Define vector compare intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93368
2020-12-22 14:08:18 +08:00
..
AsmParser [MC] Split MCContext::createTempSymbol, default AlwaysAddSuffix to true, and add comments 2020-12-21 14:04:13 -08:00
Disassembler [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
MCTargetDesc [RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output 2020-12-14 10:50:26 -08:00
TargetInfo
Utils [RISCV] Add intrinsics for vsetvli instruction 2020-12-18 12:10:09 -08:00
CMakeLists.txt [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block. 2020-12-11 10:35:37 -08:00
RISCV.h [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block. 2020-12-11 10:35:37 -08:00
RISCV.td [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block. 2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp [RISCV] Initial infrastructure for code generation of the RISC-V V-extension 2020-12-04 11:39:30 -08:00
RISCVFrameLowering.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVFrameLowering.h
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp [Target] Use llvm::erase_if (NFC) 2020-12-20 17:43:22 -08:00
RISCVInstrInfo.h
RISCVInstrInfo.td [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions 2020-12-10 19:25:51 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions 2020-12-10 19:25:51 +00:00
RISCVInstrInfoC.td [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
RISCVInstrInfoD.td [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td [RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU. 2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td Recommit "[RISCV] Add intrinsics for vfmv.f.s and vfmv.s.f" 2020-12-18 11:19:05 -08:00
RISCVInstrInfoVPseudos.td [RISCV] Define vector compare intrinsics. 2020-12-22 14:08:18 +08:00
RISCVInstrInfoZfh.td [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp [RISCV] Add intrinsics for vsetvli instruction 2020-12-18 12:10:09 -08:00
RISCVISelDAGToDAG.h
RISCVISelLowering.cpp [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen. 2020-12-18 11:43:38 -08:00
RISCVISelLowering.h [RISCV] Add intrinsics for vmv.x.s and vmv.s.x 2020-12-18 10:30:48 -08:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions. 2020-12-15 12:56:49 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp [RISCV] Define the remaining vector fixed-point arithmetic intrinsics. 2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td [RISCV] Define the remaining vector fixed-point arithmetic intrinsics. 2020-12-20 22:57:07 -08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetMachine.h [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h