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1bb14916f2
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
165 lines
4.9 KiB
LLVM
165 lines
4.9 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
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@var = global i32 0, align 4
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; CHECK-LABEL: @test_i128_align
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define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
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store i32 %after, i32* @var, align 4
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; CHECK-DAG: str w4, [{{x[0-9]+}}, :lo12:var]
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ret i128 %arg
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; CHECK-DAG: mov x0, x2
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; CHECK-DAG: mov x1, x3
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}
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; CHECK-LABEL: @test_i64x2_align
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define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
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store i32 %after, i32* @var, align 4
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; CHECK-DAG: str w3, [{{x[0-9]+}}, :lo12:var]
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ret [2 x i64] %arg
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; CHECK-DAG: mov x0, x1
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; CHECK: mov x1, x2
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}
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@var64 = global i64 0, align 8
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; Check stack slots are 64-bit at all times.
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define void @test_stack_slots([8 x i64], i1 %bool, i8 %char, i16 %short,
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i32 %int, i64 %long) {
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; CHECK-LABEL: test_stack_slots:
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; CHECK-DAG: ldr w[[ext1:[0-9]+]], [sp, #24]
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; CHECK-DAG: ldrh w[[ext2:[0-9]+]], [sp, #16]
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; CHECK-DAG: ldrb w[[ext3:[0-9]+]], [sp, #8]
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; CHECK-DAG: ldr x[[ext4:[0-9]+]], [sp, #32]
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; CHECK-DAG: ldrb w[[ext5:[0-9]+]], [sp]
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; CHECK-DAG: and x[[ext5]], x[[ext5]], #0x1
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64, align 8
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; CHECK: str x[[ext5]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = zext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64, align 8
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; CHECK: str x[[ext3]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64, align 8
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; CHECK: str x[[ext2]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64, align 8
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; CHECK: str x[[ext1]], [{{x[0-9]+}}, :lo12:var64]
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store volatile i64 %long, i64* @var64, align 8
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; CHECK: str x[[ext4]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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; Make sure the callee does extensions (in the absence of zext/sext
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; keyword on args) while we're here.
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define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
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%ext_bool = zext i1 %bool to i64
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store volatile i64 %ext_bool, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_char = sext i8 %char to i64
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store volatile i64 %ext_char, i64* @var64
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; CHECK: sxtb [[EXT:x[0-9]+]], w1
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_short = zext i16 %short to i64
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store volatile i64 %ext_short, i64* @var64
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; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
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; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
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%ext_int = zext i32 %int to i64
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store volatile i64 %ext_int, i64* @var64
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; CHECK: mov w[[EXT:[0-9]+]], w3
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; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
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ret void
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}
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declare void @variadic(i32 %a, ...)
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; Under AAPCS variadic functions have the same calling convention as
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; others. The extra arguments should go in registers rather than on the stack.
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define void @test_variadic() {
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call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
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; CHECK: fmov d0, #2.0
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; CHECK: mov w1, #1
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; CHECK: bl variadic
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ret void
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}
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; We weren't marking x7 as used after deciding that the i128 didn't fit into
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; registers and putting the first half on the stack, so the *second* half went
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; into x7. Yuck!
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define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
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; CHECK-LABEL: test_i128_shadow:
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; CHECK: ldp x0, x1, [sp]
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ret i128 %sp
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}
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; This test is to check if fp128 can be correctly handled on stack.
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define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) {
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; CHECK-LABEL: test_fp128:
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; CHECK: ldr {{q[0-9]+}}, [sp]
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ret fp128 %arg1
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}
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; Check if VPR can be correctly pass by stack.
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define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {
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entry:
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; CHECK-LABEL: test_vreg_stack:
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; CHECK: ldr {{q[0-9]+}}, [sp]
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ret <2 x double> %varg_stack;
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}
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; Check that f16 can be passed and returned (ACLE 2.0 extension)
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define half @test_half(float, half %arg) {
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; CHECK-LABEL: test_half:
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; CHECK: mov v0.16b, v1.16b
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ret half %arg;
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}
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; Check that f16 constants are materialized correctly
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define half @test_half_const() {
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; CHECK-LABEL: test_half_const:
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; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]
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ret half 0xH4248
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}
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; Check that v4f16 can be passed and returned in registers
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define <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
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; CHECK-LABEL: test_v4_half_register:
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; CHECK: mov v0.16b, v1.16b
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ret <4 x half> %arg;
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}
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; Check that v8f16 can be passed and returned in registers
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define <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
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; CHECK-LABEL: test_v8_half_register:
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; CHECK: mov v0.16b, v1.16b
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ret <8 x half> %arg;
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}
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; Check that v4f16 can be passed and returned on the stack
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define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {
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; CHECK-LABEL: test_v4_half_stack:
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; CHECK: ldr d0, [sp]
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ret <4 x half> %arg;
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}
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; Check that v8f16 can be passed and returned on the stack
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define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {
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; CHECK-LABEL: test_v8_half_stack:
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; CHECK: ldr q0, [sp]
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ret <8 x half> %arg;
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}
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