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d643ef9468
Summary: Add support for lowering various BFloat related SelDAG nodes: - load/store (ldrh/strh) - concat - dup/duplane - bitconvert/bitcast - insert_subvector/insert_subreg This patch is part of a series implementing the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile Reviewers: ab, t.p.northover, john.brawn, fpetrogalli, sdesmalen, LukeGeeson Reviewed By: fpetrogalli Subscribers: LukeGeeson, pbarrio, kristof.beyls, hiraditya, danielkiss, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79712
39 lines
1021 B
LLVM
39 lines
1021 B
LLVM
; RUN: llc < %s -asm-verbose=0 -mtriple=arm64-eabi | FileCheck %s
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; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-eabi | FileCheck %s
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; test argument passing and simple load/store
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define bfloat @test_load(bfloat* %p) nounwind {
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; CHECK-LABEL: test_load:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load bfloat, bfloat* %p, align 16
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ret bfloat %tmp1
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}
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define <4 x bfloat> @test_vec_load(<4 x bfloat>* %p) nounwind {
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; CHECK-LABEL: test_vec_load:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ret
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%tmp1 = load <4 x bfloat>, <4 x bfloat>* %p, align 16
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ret <4 x bfloat> %tmp1
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}
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define void @test_store(bfloat* %a, bfloat %b) nounwind {
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; CHECK-LABEL: test_store:
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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store bfloat %b, bfloat* %a, align 16
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ret void
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}
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; Simple store of v4bf16
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define void @test_vec_store(<4 x bfloat>* %a, <4 x bfloat> %b) nounwind {
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; CHECK-LABEL: test_vec_store:
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; CHECK-NEXT: str d0, [x0]
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; CHECK-NEXT: ret
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entry:
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store <4 x bfloat> %b, <4 x bfloat>* %a, align 16
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ret void
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}
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