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https://github.com/RPCS3/llvm-mirror.git
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516e87f87d
Summary: This prevents regressions in next patch, and somewhat recovers from the regression to AMDGPU test in D62223. It is indeed not great that we leave vector decrement, don't transform it into vector add all-ones.. https://rise4fun.com/Alive/ZRl This is a recommit, originally committed in rL361852, but reverted to investigate test-suite compile-time hangs, and then reverted in rL362109 to fix missing constant folds that were causing endless combine loops. Reviewers: RKSimon, craig.topper, spatel, arsenm Reviewed By: RKSimon, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, javed.absar, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62263 llvm-svn: 362144
85 lines
2.4 KiB
LLVM
85 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define i32 @PR39657(i8* %p, i64 %x) {
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; CHECK-LABEL: PR39657:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x1
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; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
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; CHECK-NEXT: ret
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%sh = shl i64 %x, 2
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%mul = xor i64 %sh, -4
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
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%bc = bitcast i8* %add.ptr to i32*
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%load = load i32, i32* %bc, align 4
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ret i32 %load
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}
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define i32 @add_of_not(i32 %x, i32 %y) {
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; CHECK-LABEL: add_of_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w1
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; CHECK-NEXT: add w0, w8, w0
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; CHECK-NEXT: ret
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%t0 = sub i32 %x, %y
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%r = add i32 %t0, -1
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ret i32 %r
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}
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define i32 @add_of_not_decrement(i32 %x, i32 %y) {
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; CHECK-LABEL: add_of_not_decrement:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w1
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; CHECK-NEXT: add w0, w8, w0
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; CHECK-NEXT: ret
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%t0 = sub i32 %x, %y
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%r = sub i32 %t0, 1
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ret i32 %r
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}
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define <4 x i32> @vec_add_of_not(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: vec_add_of_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v1.16b, v1.16b
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; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%t0 = sub <4 x i32> %x, %y
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%r = add <4 x i32> %t0, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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define <4 x i32> @vec_add_of_not_decrement(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: vec_add_of_not_decrement:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v1.16b, v1.16b
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; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%t0 = sub <4 x i32> %x, %y
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%r = sub <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %r
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}
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define <4 x i32> @vec_add_of_not_with_undef(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: vec_add_of_not_with_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t0 = sub <4 x i32> %x, %y
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%r = add <4 x i32> %t0, <i32 -1, i32 undef, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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define <4 x i32> @vec_add_of_not_with_undef_decrement(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: vec_add_of_not_with_undef_decrement:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t0 = sub <4 x i32> %x, %y
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%r = add <4 x i32> %t0, <i32 1, i32 undef, i32 1, i32 1>
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ret <4 x i32> %r
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}
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